Embedded C/C++ Engineer for ML Accelerator Systems

Amazon Web Services (AWS); Austin (TX); On-site; USD 144,000 - 194,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

RSUs (restricted stock units)

Job summary

Annapurna Labs (a unit within AWS) is seeking an experienced C/C++ engineer to join our embedded software team. You will develop bare metal firmware that executes neural network models on our custom ASIC-based ML accelerators, co-design hardware with RTL teams, and help deliver high-performance ML infrastructure.

The role combines hardware/software co-design at the intersection of firmware and silicon, with opportunities to influence architecture and validation.

Qualifications

• 3+ years of non-internship professional software development experience.
• 2+ years of design or architecture (design patterns, reliability and scaling) of new and existing systems.
• 2+ years of programming using a modern language such as Java, C++, or C#, with OO design experience.
• 3+ years of full software development life cycle, including coding standards, code reviews, source control, build, testing and operations.
• Bachelor's degree in computer science or equivalent.
• Experience in computer architecture.
• Experience writing firmware or bare metal software using C/C++.

Responsibilities

• Software / hardware architecture and co-design
• Bare metal C/C++ software development, testing, debug, and performance improvements
• Test suite and infrastructure development
• Developing software which can be maintained, improved upon, documented, tested, and reused
• Close collaboration with RTL designers, design verification engineers, other software teams and customers

Skills

C/C++

Java

C#

OO design

Education

Bachelor's degree in computer science

Job description

Annapurna Labs (a unit within AWS) is seeking an experienced C/C++ engineer to join our embedded software team. You will develop bare metal firmware that executes neural network models on our custom ASIC-based ML accelerators, co-design hardware with RTL teams, and help deliver high-performance ML infrastructure.

The role combines hardware/software co-design at the intersection of firmware and silicon, with opportunities to influence architecture and validation.