DMTS Design Engineer – Memory Architecture Leader

Micron Technology, Inc; Boise (ID); On-site; USD 208,000 - 416,000; Full time

Job summary

Micron Technology, Inc. is seeking a Distinguished Member of Technical Staff (DMTS) Design Engineer to advance memory innovation in DRAM systems. Based in Boise, ID or San Jose, CA, you will shape architecture, drive performance improvements, and mentor teams in a technically visible leadership role.

The role anchors the Technical Leadership Program, requiring deep knowledge of DDR4/5 and memory systems, with cross-functional collaboration across firmware, hardware, and product groups.

Qualifications

• Bachelor’s or Master’s degree in EE/CE/CS or related field.
• Strong understanding of DDR memory architecture including timing and signaling.
• Experience analyzing memory systems at device and system levels.
• Knowledge of high-speed I/O, electrical margins, and memory power/thermal characteristics.
• Proven ability to evaluate tradeoffs and communicate data-driven recommendations.

Responsibilities

• Analyze DDR4, DDR5, LPDDR, and emerging memory technologies across electrical, thermal, power, and performance dimensions.
• Identify performance gaps and evaluate tradeoffs in cost, latency, bandwidth, and efficiency.
• Partner with architecture and product teams to translate analysis into actionable design guidance.
• Drive multi-functional alignment with firmware, validation, hardware, and business partners.
• Deliver clear technical assessments to guide future memory strategy.
• Use AI tools to build models and summarize data for distribution and analysis.

Skills

DDR memory architecture

Memory systems analysis

High-speed I/O

Data-driven recommendations

Memory power & thermal

DDR4/5 experience

Education

Bachelor’s or Master’s degree in EE/CE/CS or related field

Tools

AI modeling tools

Job description

Micron Technology, Inc. is seeking a Distinguished Member of Technical Staff (DMTS) Design Engineer to advance memory innovation in DRAM systems. Based in Boise, ID or San Jose, CA, you will shape architecture, drive performance improvements, and mentor teams in a technically visible leadership role.

The role anchors the Technical Leadership Program, requiring deep knowledge of DDR4/5 and memory systems, with cross-functional collaboration across firmware, hardware, and product groups.