Memory Architect

Hewlett Packard Enterprise; Spring (TX); On-site; USD 147,050 - 230,850; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Parental leave

Holidays

Paid vacation

Job summary

Hewlett Packard Enterprise is seeking a Memory Architect in Spring, TX to lead memory architecture and placement decisions for AI PC designs. You will analyze bandwidth, latency, and cache efficiency while guiding cross-functional teams across silicon, firmware, and OS.

The role emphasizes optimizing memory configurations and measuring product performance. The ideal candidate has deep memory design experience, FPGA familiarity, and a background in electrical engineering.

Qualifications

• Memory architectures & dependencies analysis for AI PC designs.
• Experience with memory placements, workload optimizations, and tradeoff analysis.

Responsibilities

• Drive footprint optimization vs bandwidth/latency tradeoffs.
• Model workload sensitivity (latency, bandwidth, cache efficiency).
• Optimize for AI, graphics, and productivity workloads.
• Collaborate with silicon, firmware, and OS teams on memory architectures and design.
• Review designs for compliance with standards and track performance metrics.

Skills

Memory design

Hardware design

Hardware architecture

FPGA

Computer engineering

Computer science

Debugging

Electrical engineering

Electronic engineering

Physics

PCB design

Schematic capture

Systems design

MATLAB

Printed circuit board

Vverifications

Oscilloscope

Education

Electrical Engineering degree

Tools

Oscilloscope

MATLAB

Job description

## Memory ArchitectApplylocations: Spring, Texas, United States of America: Taipei, Taipei City, Taiwan Regiontime type: Full timeposted on: Posted Todayjob requisition id: 3163828Memory Architect**Description -****Job Summary** • This role will apply knowledge of memory architectures & dependencies to propose & explore new memory concepts including placements, workload optimizations, & tradeoff analysis to AI PC designs. This role will provide guidance & tradeoff analysis for given memory configurations and workloads with a goal to reduce memory requirements/dependencies for AI PC designs. This role is responsible for developing organization-wide architectures and methodologies, identifying and evaluating emerging memory technologies and partnerships, and aligning these with technology roadmaps and business value. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related performance metrics. The role leverages functional expertise to shape strategy and policy, facilitating the realization of operational and strategic plans. **Responsibilities*** Drive footprint optimization vs. bandwidth/latency tradeoffs* Model and analyze workload sensitivity (latency vs. bandwidth vs. cache efficiency)* Optimize for AI, graphics, and productivity workload mixes* Partner with silicon, firmware, and OS teams on memory architectures, placement, & design* Influence supplier/IHV roadmaps (JEDEC, memory vendors)* Develops organization-wide architectures and methodologies for electrical hardware design and development across multiple platforms and organizations.* Leads part qualification processes through implementation of product quality plans, equipment inspections, factory witness testing, and manufacturing process qualifications.* Identifies and evaluates new technologies, innovations, and outsourced development partner relationships for alignment with technology roadmap and business value.* Drives integration of new technologies into projects and activities in the electrical hardware design organization.* Reviews and evaluates designs and project activities for compliance with technology and development guidelines and standards; provides tangible feedback to improve product quality.* Leads overall tracking and reporting of various electrical/hardware product related performance metrics and reports against the same.* Exercises independent judgment in resolving business issues and establishing functional policies for guidance.* Provides domain-specific expertise and overall electrical/electronic hardware and platform leadership and perspective to cross-organization projects, programs, and activities.* Leverages functional expertise in guiding strategy and setting functional policy and direction, while helping the team in realization of these operational and strategic plans.* Provides guidance and mentoring to less- experienced staff members to set an example of electrical hardware design and development, innovation, and excellence.****Education & Experience** Recommended** • Four-year or Graduate Degree in Electrical Engineering, or any other related discipline or commensurate work experience or demonstrated competence. • Typically has 10+ years of work experience, preferably in electrical design and tools, software packages, architecture of electronic hardware, or a related field. **Preferred Certifications** NA **Knowledge & Skills** • Memory design • Computer Engineering • Computer Science • Debugging • Electrical Engineering • Electronic Engineering • Electronics • Field-Programmable Gate Array (FPGA) • Hardware Architecture • Hardware Design • MATLAB • New Product Development • Oscilloscope • Physics • Printed Circuit Board • Schematic Capture • Simulations • Systems Design **Cross-Org Skills** • Effective Communication • Results Orientation • Learning Agility • Digital Fluency • Customer Centricity **Impact & Scope** • Impacts large functions and leads large, cross-division functional teams or projects. **Complexity** • Provides highly innovative solutions to complex problems within established policy. **Disclaimer** • This job description describes the general nature and level of work performed in this role. It is not intended to be an exhaustive list of all duties, skills, responsibilities, knowledge, etc. These may be subject to change and additional functions may be assigned as needed by management.The pay range for this role is $147,050 to $230,850 USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.Benefits:HP offers a comprehensive benefits package for this position, including: \* Health insurance \* Dental insurance \* Vision insurance \* Long term/short term disability insurance \* Employee assistance program \* Flexible spending account \* Life insurance \* Generous time off policies, including; \* 4-12 weeks fully paid parental leave based on tenure \* 11 paid holidays \* Additional flexible paid vacation and sick leave (US benefits overview [https://hpbenefits.ce.alight.com/])The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.**Job -**Engineering**Schedule -**Full time**Shift -**No shift premium (United States of America)**Travel -****Relocation -****Equal Opportunity Employer (EEO) -**HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).