Memory Architect

HP; Houston (TX); On-site; USD 147,000 - 231,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Long term disability insurance

Life insurance

Generous paid time off

Job summary

HP Memory Architect is responsible for shaping organization-wide memory architectures and methodologies to reduce memory dependencies in AI PC designs. The role guides tradeoffs, analyzes workloads, and aligns memory technology with HP roadmaps and business value.

It requires senior-level expertise in memory design, FPGA, hardware architecture and collaboration with silicon, firmware, and OS teams to deliver measurable performance improvements and product quality feedback.

Qualifications

• Four-year or graduate degree in Electrical Engineering, or related discipline, or equivalent experience.
• Typically has 10+ years of work experience in electrical design and tools, software, hardware architecture, or related field.

Responsibilities

• Drive memory footprint optimization by analyzing bandwidth, latency, and cache efficiency.
• Model workload sensitivity for AI, graphics, and productivity tasks.
• Partner with silicon, firmware, and OS teams on memory architectures and placements.
• Lead part qualification, quality plans, and manufacturing process qualifications.
• Evaluate new technologies and partnerships for alignment with roadmaps and value.

Skills

Memory design

Computer engineering

Computer science

Debugging

Electrical engineering

Electronic engineering

FPGA

Hardware architecture

Hardware design

MATLAB

New product development

Oscilloscope

Physics

Printed circuit board

Schematic capture

Simulations

Systems design

Education

Electrical Engineering degree

Tools

MATLAB

Oscilloscope

Schematic Capture

Simulations

Job description

Memory Architect Description - Job Summary

This role will apply knowledge of memory architectures & dependencies to propose & explore new memory concepts including placements, workload optimizations, & tradeoff analysis to AI PC designs. This role will provide guidance & tradeoff analysis for given memory configurations and workloads with a goal to reduce memory requirements/dependencies for AI PC designs. This role is responsible for developing organization-wide architectures and methodologies, identifying and evaluating emerging memory technologies and partnerships, and aligning these with technology roadmaps and business value. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related performance metrics. The role leverages functional expertise to shape strategy and policy, facilitating the realization of operational and strategic plans.

Responsibilities

Drive footprint optimization vs. bandwidth/latency tradeoffs. Model and analyze workload sensitivity (latency vs. bandwidth vs. cache efficiency). Optimize for AI, graphics, and productivity workload mixes. Partner with silicon, firmware, and OS teams on memory architectures, placement, & design. Influence supplier/IHV roadmaps (JEDEC, memory vendors). Develop organization-wide architectures and methodologies for electrical hardware design and development across multiple platforms and organizations. Leads part qualification processes through implementation of product quality plans, equipment inspections, factory witness testing, and manufacturing process qualifications. Identifies and evaluates new technologies, innovations, and outsourced development partner relationships for alignment with technology roadmap and business value. Drives integration of new technologies into projects and activities in the electrical hardware design organization. Reviews and evaluates designs and project activities for compliance with technology and development guidelines and standards; provides tangible feedback to improve product quality. Leads overall tracking and reporting of various electrical/hardware product related performance metrics and reports against the same. Exercises independent judgment in resolving business issues and establishing functional policies for guidance. Provides domain-specific expertise and overall electrical/electronic hardware and platform leadership and perspective to cross-organization projects, programs, and activities. Leverages functional expertise in guiding strategy and setting functional policy and direction, while helping the team in realization of these operational and strategic plans. Provides guidance and mentoring to less- experienced staff members to set an example of electrical hardware design and development, innovation, and excellence.

Education & Experience Recommended

• Four-year or Graduate Degree in Electrical Engineering, or any other related discipline or commensurate work experience or demonstrated competence.
• Typically has 10+ years of work experience, preferably in electrical design and tools, software packages, architecture of electronic hardware, or a related field.

Preferred Certifications

NA

Knowledge & Skills

• Memory design
• Computer Engineering
• Computer Science
• Debugging
• Electrical Engineering
• Electronic Engineering
• Electronics
• Field-Programmable Gate Array (FPGA)
• Hardware Architecture
• Hardware Design
• MATLAB
• New Product Development
• Oscilloscope
• Physics
• Printed Circuit Board
• Schematic Capture
• Simulations
• Systems Design

Cross‑Org Skills

• Effective Communication
• Results Orientation
• Learning Agility
• Digital Fluency
• Customer Centricity

Impact & Scope

Impacts large functions and leads large, cross‑division functional teams or projects.

Complexity

Provides highly innovative solutions to complex problems within established policy.

Disclaimer

This job description describes the general nature and level of work performed in this role. It is not intended to be an exhaustive list of all duties, skills, responsibilities, knowledge, etc. These may be subject to change and additional functions may be assigned as needed by management.

Compensation & Benefits

The pay range for this role is $147,050 to $230,850 USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job‑related knowledge, skills, and experience.

Benefits

• Health insurance
• Dental insurance
• Vision insurance
• Long term/short term disability insurance
• Employee assistance program
• Flexible spending account
• Life insurance
• Generous time off policies, including; 4-12 weeks fully paid parental leave based on tenure
• 11 paid holidays
• Additional flexible paid vacation and sick leave (US benefits overview https://hpbenefits.ce.alight.com/)

Job Attributes

• Job - Engineering Schedule - Full time
• Shift - No shift premium (United States of America)
• Travel - Relocation
• Equal Opportunity Employer (EEO) - HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).
• Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested.
• The information obtained will be kept in strict confidence.
• For more information, review HP’s EEO Policy or read about your rights as an applicant under the law here: “Know Your Rights: Workplace Discrimination is Illegal”