Senior Principal / Distinguished Engineer – SerDes Analog/Mixed-Signal Design

Upscale, Inc.; United States; On-site; USD 261,000 - 297,000; Full time

Job summary

Upscale, Inc. is building next-generation SerDes technology to enable bandwidth and efficiency for future AI infrastructure.

We seek exceptional analog and mixed-signal engineers to drive high-performance circuits and shape the technical direction of our SerDes platform. As a Senior Principal / Distinguished Engineer, you will lead design efforts across architecture, analog/mixed-signal, and digital teams, guide silicon implementation from concept to validation, and mentor engineers to deliver

Qualifications

• Advanced degree in Electrical Engineering or related field with deep experience in analog/mixed-signal IC design.
• Proven track record delivering 100G+ SerDes or similar high-speed IP.
• Strong debugging and silicon validation skills with cross-functional impact.
• Excellent communication and ability to influence engineering decisions across teams.

Responsibilities

• Lead the design and implementation of complex high-speed analog/mixed-signal circuits and SerDes IP.
• Define circuit approaches to meet performance, power, area, and robustness targets for 100G+ SerDes PHYs.
• Resolve challenging circuit-design issues through first-principles analysis, modeling, and silicon study.
• Lead technical reviews and influence decisions across architecture, analog/mixed-signal, digital, layout, and validation.
• Drive design closure across post-layout verification, optimization, and silicon correlation.
• Identify opportunities for architectural innovation, design automation, and efficiency improvements.
• Contribute to roadmaps, planning, and risk mitigation for next-generation SerDes products.
• Promote rigorous engineering practices and knowledge sharing.

Skills

Analog/mixed-signal IC design

100G+ high-speed circuit design

Circuit validation

Technical communication

Education

M.S./Ph.D. in Electrical Engineering

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking - where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI - Upscale is where you can produce meaningful work at the frontier - and operate at a high standard.

About the Role

Upscale AI is developing next-generation SerDes technology to enable the bandwidth, power efficiency, and scalability required by future AI infrastructure. We are seeking exceptional analog and mixed-signal design engineers to drive the development of complex, high-performance circuits and help shape the technical direction of our SerDes platform.

As a Senior Principal / Distinguished Engineer, you will lead technically challenging design efforts, influence circuit and subsystem architecture, and drive critical design decisions across multiple engineering disciplines. You will bring deep circuit expertise, strong engineering judgment, and a system-level perspective to deliver differentiated high-speed silicon solutions.

Responsibilities

• Lead the design and implementation of complex high-speed analog/mixed-signal circuits and critical SerDes IP.
• Define circuit approaches and design methodologies to achieve aggressive performance, power, area, and robustness objectives for 100G+ SerDes PHYs.
• Resolve the most challenging circuit-design issues through first-principles analysis, modeling, simulation, and silicon-based investigation.
• Lead technical reviews and influence decisions across architecture, analog/mixed-signal design, digital design, layout, physical design, and validation.
• Drive design closure across complex implementations, including post-layout verification, performance optimization, and silicon correlation.
• Identify opportunities for architectural innovation, design automation, and improved engineering efficiency.
• Contribute to technical roadmaps, project planning, and risk mitigation for next-generation SerDes products.
• Promote rigorous engineering practices, design quality, and knowledge sharing across the organization.

Qualifications

• M.S. or Ph.D. in Electrical Engineering or a related field.
• Extensive experience in analog/mixed-signal IC design, 100G+ high-speed circuit design, or advanced semiconductor product development.
• Demonstrated record of successfully delivering complex circuit designs from architecture through implementation and silicon validation.
• Strong debugging skills and the ability to solve ambiguous, cross-disciplinary technical problems.
• Excellent technical communication skills and the ability to influence engineering decisions across teams.

Preferred Qualifications

• Significant experience developing 100G+ high-speed SerDes or other high-performance analog/mixed-signal IP.
• Expertise in advanced CMOS process technologies and the associated challenges in circuit design, physical implementation, and variability.
• Proven expertise in one or more of the following technical areas:
• Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD).
• Phase interpolator, injection-locked oscillator, multi-phase clock generator.
• High-speed time-interleaved DAC and line driver.
• Transimpedance amplifier, CTLE, PGA, Cherry-Hooper amplifier, high-speed voltage followers.
• Time-interleaved SAR ADC, track-and-hold circuits.
• Bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, R2R DAC.
• Demonstrated success driving critical circuit blocks or subsystems to silicon with strong performance and quality.
• Experience influencing architecture and design methodology beyond an individual circuit block.
• Experience with circuit modeling, simulation automation, optimization, and silicon-to-model correlation.
• Patents, technical publications, or other evidence of meaningful technical innovation are a plus.

We are looking for technical leaders who can combine deep circuit-design expertise with architectural thinking and hands-on execution to solve the most challenging problems in next-generation high-speed connectivity.

$261,000 - $297,000 a year

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.