Senior Principal Engineer, SerDes Transmitter

Upscale, Inc.; United States; On-site; USD 261,000 - 297,000; Full time

Job summary

Upscale, Inc. is building a world-class SerDes engineering team to enable next-generation AI data center connectivity.

We seek a Senior Principal Engineer to lead SerDes transmitter design, clock generation, and advanced transmitter architectures, driving silicon-robust solutions and power-efficient performance. The candidate will own blocks from architecture through tape-out, working with cross-functional teams, and mentoring engineers to raise the technical bar in high-speed interconnect

Qualifications

• MS or PhD in Electrical Engineering or a related field, with substantial experience in high-speed analog and mixed-signal IC design.
• Experience with high-speed SerDes transmitters or comparable high-performance transmit circuits.
• Expertise in transmitter clocking, high-speed DACs, or advanced transmitter architectures.
• Strong understanding of high-speed circuit design principles, bandwidth, parasitics, jitter and power optimization.
• Experience with CMOS technologies and the challenges of implementing high-speed circuits.

Responsibilities

• Lead architecture, design, and implementation of high-speed SerDes transmitter circuits with focus on performance and power efficiency.
• Drive transmitter clock generation, distribution, timing optimization, and jitter management.
• Lead design and optimization of high-speed DACs, including time-interleaved architectures.
• Develop and optimize calibration techniques for high-speed time-interleaved DACs.
• Lead output driver designs using current-mode and voltage-mode architectures for optimal signal integrity.
• Develop bandwidth-extension techniques using inductive peaking and impedance shaping.
• Apply EM simulation and extraction tools to optimize passive structures and interconnects.
• Collaborate with cross-functional teams to optimize end-to-end link performance.
• Guide silicon validation, tape-out readiness, and design reviews.

Skills

High-speed SerDes

Transmitter clocking

High-speed DACs

Output drivers

CMOS technologies

Circuit simulation

EM analysis

Layout collaboration

Silicon validation

Technical leadership

Education

MS or PhD in Electrical Engineering or related field

Tools

Cadence EMX

Ansys HFSS

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

We are building a world-class SerDes engineering team to enable next-generation connectivity for AI data centers and high-performance computing.

We are seeking a highly accomplished Senior Principal Engineer to lead the design and development of advanced SerDes transmitter circuits. This role will drive key transmitter technologies spanning clock generation and distribution, high-speed DACs, output drivers, and innovative circuit techniques for extending bandwidth and improving power efficiency.

The ideal candidate combines deep expertise in high-speed analog and mixed-signal circuit design with hands-on experience in advanced transmitter architectures, time-interleaved DACs, high-speed clocking, and electromagnetic analysis. You will own critical design blocks from architecture and circuit development through layout collaboration, tape-out, and silicon validation, working closely with cross-functional teams to deliver leading-edge high-speed interconnect technology.

Responsibilities:

• Transmitter Design Leadership: Lead the architecture, design, and implementation of high-speed SerDes transmitter circuits targeting the next-generation high-speed interconnects, with a focus on performance, power efficiency, and silicon robustness.
• Clocking Architecture: Drive transmitter clock generation, distribution, and timing optimization, including multiphase clocking, phase alignment, jitter management, and clock-to-data timing.
• High-Speed DAC Development: Lead the design and optimization of high-speed DACs, including time-interleaved architectures, high-speed switching networks, linearity optimization, and power-efficient implementations.
• DAC Calibration: Develop and optimize calibration techniques for high-speed time-interleaved DACs, addressing timing skew, gain and offset mismatch, nonlinearities, interleaving spurs, and process-voltage-temperature variations.
• Output Driver Design: Lead the design of high-speed output drivers using both current-mode and voltage-mode architectures, optimizing output swing, impedance matching, linearity, power consumption, and signal integrity.
• Bandwidth Extension Techniques: Develop advanced circuit techniques using passive elements and networks—including inductive peaking, impedance shaping, and other bandwidth-extension methods to achieve the required high-frequency performance.
• Electromagnetic Analysis: Apply electromagnetic simulation and extraction tools, such as Cadence EMX, Ansys HFSS, or other EM tools, to analyze and optimize passive structures, interconnects, coupling, and high-frequency circuit behavior.
• Cross-Functional Integration: Collaborate with receiver, clocking, AMS layout, package, signal integrity, and silicon validation teams to optimize end-to-end link performance.
• Silicon Execution: Drive circuit simulations, design reviews, physical implementation, tape-out readiness, silicon characterization, and performance correlation to ensure successful product delivery.
• Technical Mentorship: Provide technical guidance to engineers, establish design best practices, and help raise the technical bar across the SerDes transmitter organization.

Qualifications:

• MS or PhD in Electrical Engineering or a related field, with substantial experience in high-speed analog and mixed-signal IC design.
• Strong hands-on experience designing high-speed SerDes transmitters or comparable high-performance transmit circuits.
• Demonstrated expertise in one or more of the following areas: transmitter clocking, high-speed DACs, output drivers, or advanced transmitter architectures.
• Strong understanding of high-speed circuit design principles, including bandwidth limitations, parasitic effects, jitter, noise, impedance matching, signal integrity, and power optimization.
• Experience with advanced CMOS process technologies and the challenges of implementing high-speed circuits in scaled technology nodes.
• Proficiency in circuit simulation, design optimization, and silicon debug and characterization.
• Experience collaborating with custom layout engineers and using extracted parasitics and electromagnetic simulation results to guide circuit design.
• Proven ability to lead complex technical projects, make sound engineering trade-offs, and deliver high-quality silicon.

Preferred Qualifications:

• Direct experience developing 100+G-per-lane SerDes transmitters.
• Deep expertise in time-interleaved DAC architectures and calibration techniques for high-speed transmitters.
• Experience with both current-mode and voltage-mode output driver architectures, including their trade-offs in bandwidth, linearity, output swing, power, and termination.
• Strong understanding of passive circuit design for bandwidth extension, including inductors, transformers, transmission lines, resonant networks, and impedance-shaping techniques.
• Hands-on proficiency with electromagnetic simulation and extraction tools such as Cadence EMX, Ansys HFSS, or other EM tools, including PeakView where applicable.
• Experience optimizing clock distribution, multiphase clock generation, and sampling or switching-clock quality for high-speed mixed-signal systems.
• Experience with advanced-node CMOS technologies, high-density integration, and demanding package and channel environments.
• A track record of successful silicon delivery, technical innovation, patents, or contributions to leading-edge high-speed connectivity products.

$261,000 - $297,000 a year

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us [e-mail]—we’re happy to help. Note: This inbox is only for accommodation requests.