Senior Director, SerDes

Upscale, Inc.; Kentucky; On-site; USD 306,000 - 337,000; Full time

Job summary

Upscale, Inc. is building a world-class SerDes engineering organization to enable ultra-high-speed connectivity for AI data centers and HPC.

We seek an experienced Senior Director of SerDes Engineering to lead and scale our engineering team across design centers, owning critical IP and production-ready silicon. The role combines deep technical leadership in SerDes development with organizational leadership, talent development, and cross-site execution to deliver high-impact silicon on a global

Qualifications

• MS or PhD in Electrical Engineering.
• Extensive experience in high-speed SerDes or PHY development.
• Direct experience with 100+G SerDes development.
• Proven track record building and scaling semiconductor teams.

Responsibilities

• Design Center Leadership: Establish and lead our SerDes engineering Bangalore design center, including organizational planning, hiring, resource allocation, engineering processes, and long-term capability development.
• Technical Leadership: Drive the development of advanced SerDes technologies for 100+G-per-lane and next-generation high-speed connectivity, with emphasis on receiver/clocking technologies.
• Foundation IP Ownership: Build and lead teams for critical analog and mixed-signal foundation IP, including high-speed circuit blocks, clocking circuits, receiver components, bandgap, LDO.
• Critical Module Development: Establish ownership of key SerDes modules, guiding architecture, circuit design, implementation, verification, and silicon validation.
• Talent Acquisition and Development: Recruit top engineers, develop leaders, and build a pipeline of talent.
• Engineering Excellence: Establish design methodologies, review processes, and quality practices for high-quality silicon delivery.
• Cross-Site Collaboration: Align with teams across locations, ensuring clear ownership and efficient decision-making.
• Execution and Delivery: Own plans, schedules, resources, and milestones to deliver IP and design modules.
• Technical Culture: Foster depth, accountability, collaboration, and continuous improvement.
• Organizational Scaling: Plan long-term expansion of scope and leadership.

Skills

SerDes development

Analog design

Leadership

Signal integrity

CMOS tech

Team scaling

Tape-out

Electrical engineering

Education

MS or PhD in Electrical Engineering

Tools

SPICE

Cadence

Verilog/VHDL

Job description

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

We are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.

We are seeking an experienced Senior Director of SerDes Engineering to establish, lead, and scale our engineering team across design centers. This is a strategic leadership role combining deep technical expertise in advanced SerDes development with organizational leadership, talent development, and cross-site engineering execution.

The successful candidate will build a high-performing team responsible for developing critical SerDes foundation IP and key circuit modules that enable our next-generation connectivity solutions. The team will have meaningful technical ownership, working closely with engineering leadership and design teams across locations to define architectures, develop critical IP, and deliver production-quality silicon.

We are particularly interested in leaders with strong experience in high-speed SerDes and foundation IP design who can lead and scale a collaborative, high-performance design center.

Responsibilities:

• Design Center Leadership: Establish and lead our SerDes engineering Bangalore design center, including organizational planning, hiring, resource allocation, engineering processes, and long-term capability development.
• Technical Leadership: Drive the development of advanced SerDes technologies for 100+G-per-lane and next-generation high-speed connectivity, with particular emphasis on receiver and clocking technologies.
• Foundation IP Ownership: Build and lead teams responsible for critical analog and mixed-signal foundation IP, including high-speed circuit building blocks, clocking circuits, receiver components, bandgap, LDO and other reusable technologies.
• Critical Module Development: Establish technical ownership of key SerDes modules, driving architecture, circuit design, implementation, verification, and silicon validation in close collaboration with the global engineering organization.
• Talent Acquisition and Development: Recruit exceptional engineering talent across experience levels, develop technical leaders, establish mentorship programs, and build a sustainable pipeline of future engineering talent.
• Engineering Excellence: Establish rigorous design methodologies, technical review processes, implementation standards, and quality practices to ensure high-quality, predictable silicon delivery.
• Cross-Site Collaboration: Build effective working relationships with engineering teams across locations, ensuring seamless technical communication, clear ownership boundaries, efficient decision-making, and alignment on project priorities.
• Execution and Delivery: Own engineering plans, schedules, resource commitments, and technical milestones for the organization, ensuring delivery of critical IP and design modules to support overall product objectives.
• Technical Culture: Foster a culture of technical depth, accountability, collaboration, and continuous improvement, empowering engineers to take ownership of complex design challenges.
• Organizational Scaling: Develop a long-term strategy for expanding the design center’s technical scope, engineering capacity, and leadership capabilities as the company grows.

Qualifications:

• MS or PhD in Electrical Engineering or a related field.
• Extensive experience in high-speed SerDes or PHY development, with demonstrated technical leadership in complex analog and mixed-signal IC design.
• Direct experience with 100+G SerDes development or closely related next-generation high-speed connectivity technologies.
• Strong understanding of SerDes architecture and implementation, ideally with substantial experience in receiver, clocking, or other critical analog/mixed-signal subsystems.
• Proven experience building, managing, and scaling semiconductor engineering teams, including recruiting, mentoring, performance management, and leadership development.
• Demonstrated ability to lead complex silicon development programs from architecture and circuit design through tape-out and silicon validation.
• Experience establishing engineering processes, technical review mechanisms, and organizational practices that support high-quality execution at scale.
• Excellent communication and collaboration skills, with the ability to work effectively across geographically distributed engineering organizations.
• Strong execution skills and the ability to balance technical depth, organizational development, and program delivery.

Preferred Qualifications

• Experience leading engineering teams responsible for reusable foundation IP and multiple critical analog or mixed-signal design modules.
• Experience establishing or significantly scaling a semiconductor design center.
• A strong track record of recruiting senior engineers and developing technical leaders who can independently own complex design blocks.
• Experience with advanced CMOS process technologies, high-performance analog layout, parasitic extraction, and silicon characterization.
• Familiarity with advanced packaging, high-bandwidth die-to-die interfaces, and demanding AI data center connectivity requirements.
• Experience managing global engineering teams and coordinating complex development programs across multiple sites.
• Demonstrated success building an engineering organization that delivers meaningful technical innovation and measurable product results.

$306,000 - $337,000 a year

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at [e-mail] —we’re happy to help. Note: This inbox is only for accommodation requests.