Director, ESC & Thermal Systems - 300mm Wafer Tech

ASM

Phoenix (AZ)

On-site

USD 120,000 - 180,000

Full time

14 days+

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Job summary

ASM, a leader in semiconductor technology, is seeking a senior engineer to design and qualify ESC assemblies and heater systems for 300mm wafer processing. You will define clamping parameters, evaluate dielectric materials, and mitigate contamination risks while coordinating with RF bias and power supply integration in vacuum processing chambers.

The role demands deep experience with ceramic materials, electrostatic clamping, and thermal management, plus hands-on testing with precision

Qualifications

Master's degree or PhD in Materials Science, Ceramic Engineering, or related discipline.
10+ years of experience in semiconductor capital equipment engineering with exposure to ESC or heater technologies.
Experience with 300mm wafer processing tools and OEM component qualification processes.
Knowledge of high-purity ceramic fabrication techniques (sintering, plasma spray, anodization).
Familiarity with reactive process chemistries (fluorine, chlorine plasmas) and their impact on ESC/heater materials
Solid understanding of electrostatic clamping mechanisms (Coulombic and JR force models) and their process dependencies.
Experience with ceramic materials and thin-film dielectric systems used in semiconductor equipment.
Familiarity with thermal management in vacuum environments, including radiation, conduction, and convection heat transfer.
Hands-on experience with electrical characterization equipment (LCR meters, high-voltage testers, curve tracers).
Knowledge of plasma processing systems (etch, CVD, PVD, or ALD) and their requirements for ESC performance.
Experience with FEA thermal simulation tools (ANSYS, COMSOL, or equivalent).
Strong analytical and problem-solving ability with a systematic approach to failure analysis.
Effective communication skills and ability to work in cross-functional teams.

Responsibilities

Design and develop Johnsen-Rahbek (JR) and Coulombic-type ESC assemblies for 300mm wafer processing applications.
Select and qualify dielectric materials (alumina, AlN, Y2O3) for ESC ceramic layers based on electrical, thermal, and chemical compatibility requirements.
Define ESC clamping voltage, leakage current, and chucking / dechucking performance specifications.
Characterize ESC electrical properties including volume resistivity, dielectric constant, and breakdown voltage across process temperature ranges.
Analyze and mitigate wafer backside contamination, particle generation, and arcing risks associated with ESC operation.
Support ESC integration with RF bias and DC chucking power supplies in plasma processing chambers.
Design multi-zone embedded heater assemblies for uniform wafer temperature distribution across process temperatures (room temperature to 700°C+).
Perform thermal modeling and simulation (FEA) to optimize heater layout, power density, and zone configuration.
Develop and validate closed-loop temperature control systems including thermocouple/RTD sensor selection and PID control tuning.
Characterize heater uniformity, ramp rates, and thermal response using wafer-level temperature mapping tools.
Manage thermal stress and CTE mismatch between heater, ceramic, and base plate materials to ensure long‑term reliability