Digital IC Design Engineer: High-Speed Mixed-Signal

118-WW TMG MFG OPS; Tucson (AZ); On-site; USD 90,000 - 130,000; Full time

Job summary

118-WW TMG MFG OPS is seeking a design engineer to work on high-speed mixed-signal communication circuits using state-of-the-art process technology and to design high-performance digital circuits interfacing with leading-edge analog circuitry as part of an overall system.

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging of high-speed communication chips at both circuit and behavioral levels.

Qualifications

• 3+ years of relevant experience.
• Thorough understanding of digital logic design.
• Familiarity with SystemVerilog language and simulators.
• Good understanding of analog functionality and exposure to analog IC design methods.

Responsibilities

• Define, RTL coding, simulation, synthesis, timing closure, verification and debugging of high-speed communication chips at circuit and behavioral levels.
• Prepare test methods and specifications, and assist in the preparation of data sheets and demo boards.
• Develop solutions to complex problems through assessment of various techniques and approaches.
• Plan and organize work to ensure timely completion of independent tasks with general and detailed instructions when required.
• Coordinate with a team of analog and digital design engineers to share findings and collaborate on solutions.

Skills

SystemVerilog

Digital logic design

Analog IC design methods

Problem solving

Job description

118-WW TMG MFG OPS is seeking a design engineer to work on high-speed mixed-signal communication circuits using state-of-the-art process technology and to design high-performance digital circuits interfacing with leading-edge analog circuitry as part of an overall system.

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, and debugging of high-speed communication chips at both circuit and behavioral levels.