Digital Design Manager, High-Speed SerDes & Mixed-Signal

NVIDIA Corporation; Santa Clara (CA); On-site; USD 196,000 - 311,000; Full time

Benefits offered by this job

Equity compensation

Benefits package

Job summary

NVIDIA is seeking a Senior Digital Design Manager in Santa Clara, CA, to lead a team working on mixed-signal high-speed I/O SerDes. You will drive the design of digital circuits, coordinate with analog designers and system architects, and guide front-end flows toward successful tape-outs in high-performance SoCs supporting gaming, AI, and autonomous driving.

This role demands a strong background in Verilog/SystemVerilog, RTL, UVM verification, and leadership experience, with a track record of

Qualifications

• MS or PhD in Electrical Engineering or equivalent.
• 8+ years of experience in mixed-signal design.
• 3+ years in a leadership role.
• Expertise in Verilog/SystemVerilog and RTL modeling.
• Experience with Ethernet and PCIe SerDes protocols.
• Experience with UVM and formal verification.

Responsibilities

• Lead and mentor a team of engineers in mixed-signal chip development.
• Plan and specify algorithms, evaluating PPA trade-offs.
• Guide digital circuit design including filters and calibration circuits.
• Ensure verification of digital designs with direct and random testing.
• Lead front-end design flows and coordinate with back-end for tape-outs.
• Drive silicon bring-up and performance optimization.
• Collaborate with multi-functional teams to align roadmaps with business objectives.
• Establish standard methodologies for mixed-signal design and verification.

Skills

Leadership

Verilog

SystemVerilog

RTL design

Mixed-signal

UVM

Static timing

Formal verification

Communication

SerDes knowledge

Education

MS or PhD in Electrical Engineering

Job description

NVIDIA is seeking a Senior Digital Design Manager in Santa Clara, CA, to lead a team working on mixed-signal high-speed I/O SerDes. You will drive the design of digital circuits, coordinate with analog designers and system architects, and guide front-end flows toward successful tape-outs in high-performance SoCs supporting gaming, AI, and autonomous driving.

This role demands a strong background in Verilog/SystemVerilog, RTL, UVM verification, and leadership experience, with a track record of