Digital Design Engineers - Power Management

Steinman Recruiting Associates; Dallas (TX); Hybride; USD 198 000 - 242 000; Plein temps

Avantages offerts par ce poste

Stock options

Flexible PTO

Premium benefits

Résumé du poste

Steinman Recruiting Associates is assisting a fast-growing Dallas semiconductor startup to hire a Senior to Principal Digital Design Engineer. You will own RTL development and digital architecture for advanced multiphase VR controllers and PMIC interfaces in a high-performance power delivery domain.

You will collaborate across analog, validation, and systems teams to define specifications, drive full-chip integration, and mentor junior engineers.

Qualifications

• 5+ years of IC design experience with tape-out success.
• Experience designing digital architectures for multiphase buck/boost controllers, PMICs, or VRMs.
• Familiarity with PMBus, AVSBus, I2C, I3C, or SPI; RTL development in SystemVerilog/Verilog.

Responsabilités

• Own digital architecture and RTL development for multiphase controllers and PMIC interfaces.
• Implement complex digital control loops and calibration algorithms for power stages.
• Collaborate with analog, validation, and systems engineering to define specs and integration.
• Lead verification planning with DV team and drive architectural decisions.

Connaissances

Verilog/SystemVerilog

RTL Design

Digital Architecture

PMBus

I2C/I3C/SPI

Control Theory

DSP/Control loops

Outils

PMBus

I2C

I3C

SPI

Description du poste

Join an elite, fast-growing Dallas semiconductor startup rewriting the rules of power delivery. Our client builds next-generation multiphase controllers and advanced PMICs tailored specifically for enterprise servers, AI datacenters, and hyperscaler architectures.

As an early, critical member of the engineering team, you will design the digital brains powering the world's most demanding computation clusters. The chance to work on the absolute frontier of AI infrastructure hardware.

You will:

• Own the digital architecture and RTL development (Verilog - SystemVerilog) for advanced multiphase VR controllers, high-speed telemetry, and PMIC PMBus, I2C, I3C interfaces.
• Implement complex digital control loops, state machines, and calibration algorithms for high-efficiency, ultra-fast transient power stages.
• Partner closely with analog design, validation, and systems engineering teams to define architectural specifications and achieve full-chip integration.
• Collaborate with the DV team to develop block-level and chip-level verification plans, reviewing coverage metrics and debugging chip-level behaviors.
• Proactively solve cross-functional bottlenecks. Build structures from the ground up rather than just following existing blueprints.
• Leadership (Principal Level): Mentor junior engineers, drive methodologies, influence the product roadmap, and lead architectural decisions for multi-generational product lines.

What will get our attention:

• 5+ years of relevant IC design experience with a track record of tape-out success.
• Direct experience designing digital architectures for multiphase buck/boost controllers, PMICs, or VRMs.
• Familiarity with industry-standard communication protocols like PMBus, AVSBus, I2C, I3C, or SPI.
• RTL Development. SystemVerilog or Verilog for synthesis, with an emphasis on low-power design techniques and clock domain crossing (CDC) analysis.
• Control Theory. Strong grasp of digital filtering, DSP, or sampled-data control systems used in power electronics.

Digital Design Engineers (Senior to Principal Levels)

Location: On-site/hybrid in Dallas, TX.

Compensation: Base salaries to ~$220,000 DOE. Early-stage stock options with massive growth potential. Premium benefits alongside flexible PTO.

Current USA H-1B visa holders and those TN eligible are encouraged to apply.