Digital ASIC Design Intern - 12-Week Hands-on Project

MACOM; Newport Beach (CA); On-site; USD 28,000 - 65,000; Full time

Job summary

MACOM is seeking a Design Engineer Intern to join the HPA team in Newport Beach. You will work with experienced engineers, gaining hands-on experience and taking ownership of a critical project during a 12-week internship.

Mentoring, training, webinars, networking events, and a poster session are part of the program. Ideal candidates are pursuing MSEE/PhD and bring TCL, Python, Verilog RTL, and timing-analysis familiarity.

Qualifications

• Pursuing a MSEE or PhD in Digital System/ASIC design.
• Interest in learning digital ASIC place-and-route skills.
• Familiarity with TCL, Python and shell scripting for automation.
• Familiarity with static timing concepts.
• Good planning and organizational skills.
• Good interpersonal and communications skills.
• Good problem-solving and analytical skills.
• Honesty and ability to work well in a team environment.
• Willingness to learn and adapt to new concepts.

Responsibilities

• Be assigned an individual and well-defined project with set outcome goals.
• Gain hands-on experience in digital circuit design.
• Receive excellent training and ongoing supervision.
• Be invited to attend an intern webinar series.
• Attend networking/social events.
• Attend and present at Poster Session about each Interns project successes and pitfalls.
• Receive formal, written feedback.

Skills

TCL

Python

Shell scripting

Verilog RTL

Static timing concepts

Teamwork

Communication skills

Problem-solving

Honesty

Willingness to learn

Education

Pursuing MSEE or PhD in Digital System/ASIC design

Job description

MACOM is seeking a Design Engineer Intern to join the HPA team in Newport Beach. You will work with experienced engineers, gaining hands-on experience and taking ownership of a critical project during a 12-week internship.

Mentoring, training, webinars, networking events, and a poster session are part of the program. Ideal candidates are pursuing MSEE/PhD and bring TCL, Python, Verilog RTL, and timing-analysis familiarity.