DIFF/EPI Process Engineer | Yield, SPC & Tooling Leader

Tower Semiconductor Ltd.

San Antonio (TX)

On-site

USD 110,000 - 140,000

Full time

12 days ago

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Job summary

Tower Semiconductor Ltd. in Texas is seeking a skilled Process Engineer to drive optimization and continuous improvement of Diffusion and Epitaxy (DIFF/EPI) operations. You will own process health, yield optimization, and equipment performance. Collaborate with cross-functional teams to troubleshoot issues, design experiments (DOE), and lead technology transfer.

The role balances hands-on execution with analytical problem solving to meet quality and throughput targets. Required: M.S. or Ph.D.

Qualifications

MS or PhD in a relevant field, or BS with 5+ years of related experience.
Minimum of 3 years of professional experience in a semiconductor wafer fabrication environment, with diffusion or epitaxy expertise.
Proficiency in SPC, FMEA, and standard semiconductor process monitoring software tools.
Ability to design experiments, analyze data, and summarize findings for technical audiences.
MS Office Suite proficiency (Excel, Word, PowerPoint) for reporting and data visualization.

Responsibilities

Take ownership of assigned processes and set direction for improvement and operational excellence.
Collaborate with process and integration engineers to improve metrics (SPC, yield, parametrics, defects) and enable technology transfers.
Lead the selection and qualification of semiconductor processing tools.
Monitor fab performance metrics using SPC and dashboards.
Conduct root cause investigations of discrepant material and lead yield/defect improvement projects.
Develop operating specifications and provide technical training to wafer fab personnel.
Collaborate with equipment engineering to improve uptime, tool utilization, and process flexibility.
Troubleshoot process and tool excursions to minimize production impact.
Identify cost-saving opportunities and lead initiatives to reduce operating costs.
Implement advanced process control methods to improve CpK at critical levels.
Ensure proper matching and qualification of newly installed equipment for production ramp.
Develop new semiconductor manufacturing processes using DOE methodology.
Strengthen fault detection and classification strategies within responsible areas.