DFT Verification Engineer - RTL & SoC Test Architect

Delos Data; Palo Alto (CA); Hybrid; USD 160,000 - 220,000; Full time

Benefits offered by this job

Equity

401(k)

Comprehensive benefits package

Job summary

A stealth-mode startup in California is seeking an experienced DFT Verification Engineer to ensure the functionality and quality of ASIC DFT logic. This role involves building verification environments, executing coverage plans, and collaborating with design engineers. The ideal candidate holds a degree in Electrical Engineering and has over 5 years of experience, particularly with UVM methodologies and industry-standard EDA tools. The target salary is $160,000 – $220,000 annually, along with equity and benefits.

Qualifications

• 5+ years of experience in digital design verification, with at least 2 in DFT verification.
• Strong hands-on experience with UVM-based verification methodologies.
• Experience with industry-standard EDA tools.

Responsibilities

• Develop and maintain RTL verification environments using UVM.
• Create and execute coverage-driven verification plans.
• Analyze simulation results and debug complex verification issues.

Skills

UVM-based verification methodologies

SystemVerilog

Scripting (Python)

Analog and digital design fundamentals

Communication skills

Problem-solving skills

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys VCS

Siemens Tessent

Cadence Xcelium

Job description

A stealth-mode startup in California is seeking an experienced DFT Verification Engineer to ensure the functionality and quality of ASIC DFT logic. This role involves building verification environments, executing coverage plans, and collaborating with design engineers. The ideal candidate holds a degree in Electrical Engineering and has over 5 years of experience, particularly with UVM methodologies and industry-standard EDA tools. The target salary is $160,000 – $220,000 annually, along with equity and benefits.