DFT Engineer

Intelliswift - An LTTS Company; San Francisco (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

LTTS in San Francisco seeks a DFT Engineer to lead design-for-test implementations across advanced SoCs, focusing on insertion, integration, and verification of DFT features.

You'll work with MBIST, boundary scan, JTAG/IJTAG, ICL/PDL standards, and DFT tools (Siemens Tessent) to ensure testability and timing impact mitigation.

Qualifications

• Proven experience in DFT insertion, verification, and debugging.
• Knowledge of boundary scan, JTAG/IJTAG, and MBIST.
• Experience with DFT tools, preferably Siemens Tessent.

Responsibilities

• Perform DFT insertion and integration across complex SoCs.
• Lead DFT verification (DFx focus) including MBIST execution and repair flows.
• Develop and validate IJTAG, ICL and PDL descriptions; ensure compliance with standards.

Skills

DFT methodologies

DFT verification

IJTAG knowledge

Tools

Siemens Tessent

Job description

Fulltime role with L&T Technology Services (LTTS)

Summary:

DFT Engineers with strong expertise in Design-for-Test (DFT) and DFx verification to support advanced semiconductor programs. The role focuses on DFT implementation, integration, and verification of DFT features across complex SoCs.

Key Responsibilities

• Perform DFT insertion and integration for:
• Scan (including SSN architectures)
• Own DFT verification (DFx focus) across:
• Boundary Scan
• Execute MBIST implementation and repair flows, including:
• Verification and validation
• Develop and validate ICL and PDL descriptions
• Ensure compliance with IJTAG standards

Required Skills & Expertise

• Strong hands-on experience in DFT methodologies and flows

Solid knowledge of:

• Scan insertion and debugging
• MBIST architecture and verification
• Boundary scan and JTAG protocols
• Experience with IJTAG (1687), ICL, and PDL standards
• Familiarity with high-speed IO test methodologies
• Experience working with DFT tools (preferably Siemens/Tessent suite)
• Good understanding of test timing and physical design impact on DFT