DFT Design Engineer

Intel; Santa Clara (CA); Hybrid; USD 161,000 - 228,000; Full time

Job summary

Join Intel as a Design-for-Test Implementation Engineer to work on state-of-the-art silicon designs. You'll develop SoC Test Implementation plans, collaborate with top-tier customers, and enhance DFT capabilities in a dynamic environment. Required qualifications include a degree in Electrical Engineering and relevant experience in SoC DFT principles with industry-standard tools.

Benefits

Competitive Compensation Package

Health Benefits

Retirement Plans

Vacation

Qualifications

• Bachelor's or Master's degree in relevant fields required.
• 6+ years of experience for Bachelor's; 4+ for Master's.
• Industry experience with SoC DFT principles essential.

Responsibilities

• Develop SoC Test Implementation plan and DFT strategies.
• Collaborate on DFT designs for high-quality IP integration.
• Support timing closure and silicon bring-up processes.

Skills

Problem Solving

Effective Communication

Collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Mentor Graphics Tessent

Synopsys DFT Compiler

DFTMax

TetraMax

Static Timing Analysis tools

PERL

TCL/Tk

Python

Job description

Job Details:

Job Description:

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world-changing technology that enriches the lives of every person on earth. If you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Exciting opportunity to be a part of the NXNE DFT team.

The Design-for-Test (DFT) Implementation Engineer is a challenging and cutting-edge position working as part of a team to implement DFT capabilities on state-of-the-art silicon designs. You will collaborate with external tier-1 customers and internal product design teams during their ASIC design cycle, developing System-on-a-Chip (SoC) solutions using CMOS cell-based ASIC technologies, high-performance SerDes functions, embedded microprocessors, and high-speed memory interface IP.

Who You Are

Your responsibilities will include, but are not limited to:

• Developing the SoC Test Implementation plan, including strategies for DFT requirements, hierarchical test architecture, insertion of DFT structures, and generation, simulation, and validation of test patterns for DFT logic verification and HVM ATE testing.
• Supporting the Static Timing Analysis (STA) team for timing closure in DFT modes and assisting the Test Engineering team during silicon bring-up and NPI.
• Collaborating with internal Test Methodology and IP development teams.
• Developing RTL code, providing DFT timing closure support, and generating test content for DFx features like SCAN, MBIST, and BSCAN.
• Participating in the definition of architecture and microarchitecture features for DFT-designed blocks, subsystems, and SoCs.
• Creating HVM content for rapid ramp-up and production on ATE.
• Applying strategies, tools, and methods to write RTL and structural code to integrate DFT, optimizing for power, performance, area, and test coverage.
• Reviewing verification plans and driving verification of DFT designs to meet specifications.
• Ensuring correct verification of design features, resolving RTL test failures, and supporting high-quality IP and SoC integration.
• Collaborating with post-silicon and manufacturing teams to verify features on silicon, support debugging, and document learnings and improvements.
• Driving high test coverage and developing HVM content for production on ATE.

The ideal candidate will exhibit the following:

• Strong problem-solving skills and a self-starter attitude.
• Ability to independently resolve complex problems.
• Understanding of SoC DFT principles, including SCAN, BIST, and JTAG Boundary Scan.
• Effective communication and collaboration skills.
• Ability to work effectively in a cross-site team environment.

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering with 6+ years of industry experience, or
• Master's degree in the same fields with 4+ years of industry experience.

Experience in:

• SoC DFT principles, including scan, BIST, and JTAG.
• Test insertion, pattern generation, simulation, and verification.
• Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax.
• DFT architecture development and planning for SoCs.

Preferred Qualifications:

• Knowledge of manufacturing tester capabilities, ATE, and test programming.
• Experience with DFT integration of IPs like DDR, SerDes, PLLs into SoCs.
• Familiarity with Static Timing Analysis tools like Synopsys PrimeTime, constraints, and timing debugging.
• Scripting skills in PERL, TCL/Tk, Python.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Texas, Austin

Additional Locations: US, Arizona, Phoenix; US, California, Santa Clara

Business group: Xeon and Networking Engineering (XNE)

Posting Statement: All qualified applicants will receive consideration without regard to race, color, religion, sex, national origin, age, disability, or other protected characteristics.

Benefits:

Competitive compensation package including pay, stock, bonuses, and benefits such as health, retirement, and vacation. More info: https://jobs.intel.com/en/benefits

Annual Salary Range in the US: $161,230.00 - $227,620.00

Work Model: Hybrid work model allowing on-site and off-site work. Details subject to change.