Design Verification Engineer (University Grad)

Lensa; Sunnyvale (CA); On-site; USD 114,000 - 133,000; Full time

Job summary

A leading company in the tech industry is seeking a Design Verification Engineer (University Grad) in Sunnyvale, CA. The role focuses on validating new core IP implementations by collaborating with researchers and engineers, requiring strong skills in digital design verification and proficiency in various programming languages.

Qualifications

• Currently has or is in the process of obtaining a Bachelor's degree.
• Experience with ASIC development cycle.
• Experience in architecting and implementing Design Verification infrastructure.

Responsibilities

• Define and track detailed test plans for different modules.
• Collaborate with cross-functional teams to ensure design quality.
• Drive Design Verification to closure based on established metrics.

Skills

Verilog

SystemVerilog

C/C++

Python

TCL

Perl

Shell

UVM methodology

Education

Bachelor's degree in Computer Science

Bachelor's degree in Computer Engineering

Equivalent practical experience

Job description

Design Verification Engineer (University Grad)

Design Verification Engineer (University Grad)

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Lensa is the leading career site for job seekers at every stage of their career. Our client, META, is seeking professionals in Sunnyvale, CA. Apply via Lensa today!

Summary

Meta's Reality Labs (RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art graphics and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.

Required Skills

Design Verification Engineer (University Grad) Responsibilities:

• Work with researchers and architects defining verification plans for each of the different core IP.
• Define and track detailed test plans for the different modules and top levels.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
  
  

Minimum Qualifications

Minimum Qualifications:

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• Experience with ASIC development cycle.
• Experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
• Experience in one or more of the following areas along with functional verification - SystemVerilog Assertions, Formal, Emulation.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
• Interpersonal experience: cross-group and cross collaboration.
• Must obtain work authorization in the country of employment at the time of hire, and maintain ongoing work authorization during employment.
  
  

Preferred Qualifications

Preferred Qualifications:

• Demonstrated experience in development of UVM based verification environments from scratch.
• Demonstrated experience with Design verification of GPUs and Compression accelerators.
• Demonstrated experience with revision control systems like Mercurial(Hg), Git or SVN.
• Demonstrated experience with low power design.
• Master's degree in Computer Science, Computer Engineering, or a related field.
  
  

Public Compensation

$114,000/year to $133,000/year + bonus + equity + benefits

Industry: Internet

Equal Opportunity

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].

Seniority level

• Seniority level

  Entry level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  IT Services and IT Consulting

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