Senior Design Verification Engineer

QuEST Global; Sunnyvale (CA); On-site; USD 114,000 - 291,000; Full time

Job summary

QuEST Global is seeking a Talent Acquisition Lead specializing in technical recruiting in Sunnyvale, CA. This mid-senior level role requires extensive experience in debugging, developing, and implementing verification environments using modern Python, SystemVerilog, and UVM. Ideal candidates will have a strong background in advanced data structures and algorithms.

Qualifications

• 5-20 years of experience required.
• Experience in writing test cases using C/C++ for ARM cores.
• Knowledge in debugging in a mixed C and SV-UVM environment.

Responsibilities

• Understand the specs and work with designers.
• Write SV tests and debug failures.
• Implement tools using Python.

Skills

Python

Debugging

Understanding of data structures

SystemVerilog

UVM

EDL tools knowledge

Job description

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Talent Acquisition Lead @ Quest Global | Technical Recruiting

Experience Level: 5-20 years of experience

General DV skills, someone who can understand the specs, work with designers, write SV tests, and good at debug. Experience in writing testcase using c/c++ for ARM cores. Debugging test failures in C and SV-UVM mixed environment.

DV background, but more focused or specialized in the python scripting, tool implementation using python, looking for mid/sr level experience.

Proficiency in modern Python (intermediate or above)

Understanding of basic data structures and algorithms

Hands-on experience in SystemVerilog/UVM

Knowledge of UVM RAL (Register Abstraction Layer)

Experience in development in Linux based environments (Bash scripting, Makefile)

Plus:

Experience in development of UVM based verification environments

Experience in EDA tools and scripting used to build tools and flows for verification environments

Experience with revision control systems like Git or Mercurial(Hg)

JOB DESCRIPTION 4: Austin TX, San Jose CA

• Very fast paced environment.
• Excellent SV/UVM knowledge.
• Good to have: LPDDR/DDR protocol knowledge.

JOB DESCRIPTION 5: San Jose CA

• Excellent SV/UVM knowledge.
• Must have experience in PCie Gen 4/5/6

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Engineering Services and Semiconductor Manufacturing

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