Design Verification Engineer - Interface IP

The Consensus; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Housing subsidy

Relocation support

Wellness programs

Daily lunch

Unlimited compute budget

Job summary

Etched is seeking a Design Verification Engineer for the Interface IP DV team. You will validate the architecture requirements across IP subsystems and interfaces, ensuring correctness and performance from hardware to software.

The role demands creativity and deep technical ability to tackle challenging verification tasks. You will own end-to-end verification for IP subsystems, work with vendor IP configurations, and develop scalable testbenches using SystemVerilog/UVM.

Qualifications

• 5+ years of design verification experience.
• Creativity to surface corner-case bugs in complex hardware.
• Hands-on with SystemVerilog/UVM verification methodologies.
• Experience with standard IP interfaces and protocols (PCIe, Ethernet, AXI/AMBA, ARM/ARC CPUs).
• Ability to own projects in a fast-paced startup environment and collaborate cross-functionally.

Responsibilities

• Own end-to-end verification for one or more IP subsystems (PCIe, Ethernet, CPU, peripherals).
• Understand vendor IP configurations and coordinate with internal IP teams.
• Develop and maintain UVM/SystemVerilog-based verification environments for correctness and performance.
• Collaborate with integration and SoC DV teams to validate IP interactions.
• Drive coverage closure and sign-off by identifying gaps and corner cases.

Skills

SystemVerilog/UVM

IP/SoC verification

Testbench development

Debug complex bugs

Tools

UVM

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

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  End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

  
  


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  Understand vendor IP configurations and handle handshake with internal IP team

  
  


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  Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

  
  


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  Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

  
  


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  Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

  
  

You may be a good fit if you have

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  5+ years of design verification experience

  
  


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  You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

  
  


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  You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

  
  


• 
  

  You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

  
  


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  You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

  
  


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  You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.
  

  
  

Strong candidates may also have experience with

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  Experience handling vendors and integration of IP/VIP’s

  
  


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  UVM/System Verilog

  
  

Benefits

• Medical, dental, and vision packages with generous premium coverage
  
  
  
  • $500 per month credit for waiving medical benefits
  
  
  
  


• Housing subsidy of $2k per month for those living within walking distance of the office


• Relocation support for those moving to San Jose (Santana Row)


• Various wellness benefits covering fitness, mental health, and more


• Daily lunch + dinner in our office


• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.