Design Verification Engineer (GPU)

Protingent; San Jose (CA); On-site; USD 200,000 - 250,000; Full time

Job summary

Protingent is seeking a Design Verification Engineer (GPU) for a contract role in San Jose, CA. The position involves ensuring the quality of GPU architecture through innovative verification techniques and collaboration with design teams. Candidates should possess a BS in Computer Engineering and extensive experience in verification methodologies.

Benefits

Competitive salaries

Insurance plan options

Education/certification reimbursement

Paid Time Off (PTO)

401k plan

Qualifications

• 5+ years of industry experience in a design verification role.
• Proficient in System Verilog/UVM/OVM, and OOP/C++.
• Deep understanding of constrained randomization.

Responsibilities

• Build verification environments and test plans.
• Develop assertions and checks to optimize isolation time.
• Analyze failing tests to root cause.

Skills

System Verilog

UVM

OVM

OOP

C++

Python

Perl

Education

BS in Computer Engineering

MS CE/EE

Job description

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Job Description

Job Title: Design Verification Engineer (GPU)

Position Description: Protingent Staffing has an exciting contract opportunity for Design Verification Engineer (GPU) with our client located in San Jose, CA.

Job Description: As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.

Job Responsibilities:

• Work with architects and designers to build verification environments and test plans
• Craft functional verification coverage strategy to ensure complete test suite implementation
• Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
• Analyze failing tests to root cause along, working with RTL and reference modeling teams
• Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
• Examine code coverage results, identifying exclusions and improving stimulus
• Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics.
  
  
  

Job Qualifications:

• BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
• Proficient in System Verilog/UVM/OVM, and OOP/C++
• Deep understanding of constrained randomization and the development of efficient test suites
• Experience with code coverage and functional coverage-driven verification methodology.
• Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
• Working knowledge of scripting languages such as Python or Perl
• Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
• Experience of GPU or CPU.
  
  
  

Nice To Have:

• MS CE/EE with 5+ years of industry experience in verification
• Good verbal and written communication skills
  
  
  

Job Details:

• Contract: 6 months
• Pay Range: $100- $130 an hour.
• Location: San Jose, CA (Onsite)
  
  
  

Benefits Package: Protingent offers competitive salaries, insurance plan options (HDHP plan or POS plan), education/certification reimbursement, pre-tax commuter benefits, Paid Time Off (PTO), and an administered 401k plan.

About Protingent: Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation — from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We’re passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Job function

  Engineering and Information Technology

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