Design Verification Engineer | BCP

Texas Instruments Incorporated; Knoxville (TN); On-site; USD 110,000 - 150,000; Full time

Job summary

Texas Instruments Incorporated is seeking a Design Verification Engineer to join the Analog Power Products organization in Knoxville. You will develop and execute verification strategies to ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive, and consumer applications.

You will work across the full verification cycle—from planning and building test benches to running coverage regressions and tracking closure—collaborating closely with

Qualifications

• Develop detailed verification plans in collaboration with the design and systems teams.
• Create test benches, tests, and simulations at RTL and gate-level.
• Perform coverage regressions and track closure against goals.
• Track and communicate verification status and issues.
• Develop scripts and use regression tools to automate flows.
• Contribute to continuous improvements in DV methodology, tools, and flows.

Responsibilities

• Develop detailed verification plans while coordinating with design and system teams.
• Build test benches, tests, and RTL/GLS simulations for the full chip.
• Run coverage regressions to ensure defined coverage goals are met.
• Track and communicate verification status, issues, and risk.
• Develop scripts and automate regression analysis workflows.
• Improve DV methodology and DV toolchain based on lessons learned.

Skills

DV verification

Test benches

RTL

GLS

Coverage analysis

Scripting

Job description

Change the world. Love your job.

Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Knoxville. In this role, you will develop and execute verification strategies that ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive, and consumer applications.

As a Design Verification Engineer, you will work across the full verification cycle – from developing detailed verification plans and building test benches through running coverage regressions, tracking closure, and contributing to continuous improvements in DV methodology – collaborating closely with digital design and systems engineering teams.

Responsibilities include:

• Develop detailed verification plans while working closely with the design and system team to ensure first-pass silicon success
• Develop test benches, tests, and simulations at RTL and gate-level (GLS) for the entire chip
• Run coverage regressions to meet defined coverage goals
• Track and communicate verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods, and flows