Design Verification Engineer

Texas Instruments Incorporated

Knoxville (TN)

On-site

USD 110,000 - 160,000

Full time

14 days+

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Job summary

Texas Instruments Incorporated in Knoxville, TN is seeking a Design Verification Engineer to drive verification strategies for analog and mixed-signal ICs used in industrial, automotive and consumer applications. You will develop verification plans, build test benches, and run RTL/GLS simulations.

You will work with analog, digital and systems teams to ensure first-pass silicon success, track coverage, and contribute to DV methodology improvements.

Responsibilities

  • Developing detailed verification plans while working closely with the design and system team to ensure first pass silicon success
  • Developing test benches, tests and simulations at RTL and GLS
  • Development of SystemVerilog and Verilog-AMS behavioral models for analog circuits
  • Work with regression tools and develop scripts to submit cases for regression analysis
  • Running coverage regressions to meet the defined coverage goals
  • Tracking and communicating verification status, issues and concerns
  • Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Job description

Change the world. Love your job.

Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Knoxville, TN. In this role, you will develop and execute verification strategies that ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive and consumer applications.

As a Design Verification Engineer, you will work across the full verification cycle – from developing detailed verification plans and building test benches through running coverage regressions, tracking closure and contributing to continuous improvements in DV methodology. You will collaborate closely with analog design, digital design and systems engineering teams.

As a Design Verification Engineer in this role, you will be responsible for:

  • Developing detailed verification plans while working closely with the design and system team to ensure first pass silicon success
  • Developing test benches, tests and simulations at RTL and GLS
  • Development of SystemVerilog and Verilog-AMS behavioral models for analog circuits
  • Work with regression tools and develop scripts to submit cases for regression analysis
  • Running coverage regressions to meet the defined coverage goals
  • Tracking and communicating verification status, issues and concerns
  • Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

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