Design Verification Engineer

MaximaTek; Wyoming (OH); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Targeted placement

Technical resume rebuild

Interview coaching

Job summary

MaximaTek is seeking a Design Verification Engineer (DVE) to plan, design, and execute test environments for digital and ASIC/SoC designs. You will help ensure functional design requirements are fully verified before tape-out.

You will develop verification plans, build testbenches using SystemVerilog, and drive coverage closure with UVM/OVM, collaborating with design and validation teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or related field.
• 0–5 years of experience in digital design verification, ASIC/SoC verification, or hardware systems engineering.
• Strong Verilog/SystemVerilog, UVM/OVM, and assertion-based verification (SVA) skills.
• Proficient with simulation tools (VCS/Xcelium/Questa) and scripting for automation.

Responsibilities

• Develop verification plans, testbenches, and test suites based on design specs.
• Build and maintain verification environments using SystemVerilog and UVM/OVM.
• Perform coverage analysis and drive coverage closure to targets.
• Debug RTL and gate-level failures with design engineers to root cause issues.
• Document verification processes, scripts, and regression suites to SOX-grade standards.
• Collaborate with design, architecture, and validation teams throughout the chip cycle.

Skills

Digital logic design

Verilog/SystemVerilog

UVM/OVM

SVA

Python/Perl/Bash/Tcl

Education

Bachelor’s or Master’s degree in Electrical Engineering/Computer Engineering/Microelectronics

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

About the Role: Design Verification Engineer (DVE)

We are seeking a detail-oriented Design Verification Engineer to plan, design, and execute test environments for complex digital and ASIC/SoC designs. In this role, you will act as a key contributor to product quality, ensuring that functional design requirements are fully verified and aligned with industry standards before tape-out.

Core Responsibilities

• Verification Strategy & Planning: Develop comprehensive verification plans, testbenches, and test suites based on design architecture and functional specifications.
• Testbench Development: Build, maintain, and scale advanced verification environments using SystemVerilog and methodologies like UVM/OVM.
• Feature & Coverage Verification: Write and execute test cases, perform coverage analysis (code and functional), and drive coverage closure to targeted metrics.
• Debugging & Bug Tracking: Debug complex hardware failures at RTL and gate-level, working closely with Design Engineers to isolate and resolve root causes promptly.
• Quality Assurance: Ensure all verification documentation, test scripts, and regression suites meet high-quality engineering standards and standard operating procedures.
• Cross-Functional Collaboration: Serve as a primary technical contact for design, architecture, and validation teams throughout the chip development lifecycle.

Qualifications

Education

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field (Required).

Experience

• 0–5 years of experience in digital design verification, ASIC/SoC verification, or hardware systems engineering.

Technical Skills (Required)

• Strong understanding of digital logic design principles, hardware description languages (Verilog/SystemVerilog), and verification methodologies (UVM/OVM).
• Proficiency with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa) and assertion-based verification (SVA).
• Familiarity with scripting languages (Python, Perl, Bash, or Tcl) for automation and regression setup.
• Excellent technical writing, debugging, and documentation skills.

Preferred Skills

• Experience with bus protocols (e.g., AXI, AHB, PCIe) or high-speed interface protocols.
• Knowledge of formal verification techniques and emulation platforms.
• Hands-on experience with coverage-driven constraint-random verification.

What We Offer

• Targeted Placement: Direct marketing to our network of hiring managers in the Semiconductor and Tech industries.
• Technical Resume Rebuild: Optimization of your profile to highlight technical verification expertise alongside methodology skills.
• Interview Coaching: Guidance on technical hardware interviews, SystemVerilog/UVM coding challenges, and architecture case studies.

Ready to Take the Next Step?

Email your updated resume to: [e-mail]