Design Verification Engineer

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

An established industry player is seeking a talented engineer to join their design verification team. In this role, you will be responsible for verifying high-speed mixed-signal IP designs for cutting-edge applications in 5G, AI/ML, and automotive sectors. You will engage in the complete design verification lifecycle, ensuring the highest design quality through advanced methodologies and collaboration with cross-functional teams. This opportunity offers a chance to work on innovative projects and contribute to the development of transformative technologies. If you have a passion for engineering and a desire to make an impact, this is the perfect role for you.

Benefits

Annual discretionary bonus program

Opportunity for annual RSU grants

Competitive benefits package

Qualifications

• 2+ years ASIC design verification experience required.
• Knowledge of HVL methodology like SystemVerilog/UVM is essential.

Responsibilities

• Define pre-silicon and post-silicon test plans based on design specs.
• Architect and develop the testbench using advanced verification methodologies.

Skills

ASIC design verification

SystemVerilog/UVM

Low power design verification

Formal verification

Scripting languages (Python, Perl)

Education

Master's degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

PhD in Science, Engineering

Tools

VCS

Xcellium/NCsim

Modelsim/Questa

VCFormal

Jaspergold

0In

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.

Responsibilities:

• Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.
• Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality.
• Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
• Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.
• From scratch VIP development experience for Serdes controller + PHY is an additional plus.

Minimum Qualifications:

• Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 2+ years ASIC design verification, or related work experience.
• Knowledge of a HVL methodology like SystemVerilog/UVM.
• Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.

Preferred Qualifications:

• Experience with Low power design verification, Formal verification and Gate level simulation.
• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.
• Experience in scripting languages (Python, or Perl).
• Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Additional Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Pay range and Other Compensation & Benefits:

$140,000.00 - $210,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.