Design Verification Engineer

Acceler8 Talent; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is partnering with an AI compute startup rebuilding the hardware and software stack for an AI accelerator. This senior role will own an entire verification domain from planning through functional closure, collaborating with hardware and software teams as silicon moves from pre-silicon verification to first-silicon bring-up and scale-out.

You’ll develop verification strategies, build UVM testbenches, and drive coverage models while debugging complex IP and subsystems.

Qualifications

• 5+ years of hands-on pre-silicon design-verification experience.
• End-to-end ownership from verification planning through functional closure.
• Strong SystemVerilog and UVM experience.
• Experience with block, subsystem, or full-chip verification.
• Ability to interpret specifications from both hardware and software perspectives.

Responsibilities

• Own end-to-end verification for complex IP, subsystems, or full SoCs.
• Develop verification strategies from block level through SoC and emulation.
• Build UVM testbenches, test plans, coverage models, and reusable environments.
• Debug complex functional failures and drive coverage closure.
• Collaborate with architecture, RTL, firmware, and software teams.

Skills

SystemVerilog

UVM

Pre-silicon verification

SoC verification

Debugging complex IP/SoC

Tools

Palladium

Veloce

Job description

I’m working with an AI compute startup rebuilding the hardware and software stack around extreme compute density.

The team is developing a tightly integrated platform spanning advanced silicon, packaging, firmware, compilers, kernels, and infrastructure. This role will own a major verification domain for its new AI accelerator, from planning through functional closure.

You’ll work closely with hardware and software teams, taking complex silicon from pre-silicon verification through first-silicon bring-up and scale-out.

You’ll work on problems such as:

• Owning end-to-end verification for complex IP, subsystems, or full SoCs
• Developing verification strategies from block level through SoC and emulation
• Building UVM testbenches, test plans, coverage models, and reusable environments
• Debugging complex functional failures and driving coverage closure
• Using and developing AI-assisted flows to improve verification productivity
• Partnering with architecture, RTL, firmware, and software teams

Looking for engineers who have:

• 5+ years of hands-on pre-silicon design-verification experience
• End-to-end ownership from verification planning through functional closure
• Strong SystemVerilog and UVM experience
• Experience with block, subsystem, or full-chip verification
• A track record of debugging complex IP or SoC designs
• The ability to interpret specifications from both hardware and software perspectives
• Experience defining clear milestones and delivering against aggressive silicon schedules

Nice to have:

• CPU-subsystem or IP-integration verification
• Palladium, Veloce, or similar emulation experience
• RISC-V knowledge
• Post-silicon bring-up and debug experience

This is a senior individual-contributor opportunity with ownership of an entire verification domain for a new AI computing platform.