Design Verification Engineer

Optimalsemi; Dallas (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Fiori Technology Solutions is actively seeking a Design Verification Engineer to join our growing team in Dallas. The role focuses on digital verification for complex SoCs with ARM cores, peripherals, and memory architectures, ensuring robust verification across the development flow.

The candidate will work in a collaborative, cross-geography environment, with exposure to mixed-signal aspects and UVM testcase development.

Qualifications

• Bachelor’s or Master’s degree in related engineering field.
• Ability to work independently and across geographies.
• 3+ and 8+ years industry experience implied by role requirements.

Responsibilities

• Digital verification for complex SoC with MCUs (ARM CM0+/CM3/CM4/CM33) with peripherals and memory architectures.
• Familiar with SoC development flow and environments; mixed signal circuits (ADC/DAC, clocks, power management).
• Basic understanding of UVM and testcase development; mixed simulation environment (digital + analog).

Skills

SoC verification

Digital verification

UVM exposure

Education

Bachelor's/Master's in engineering

Tools

Cadence tools

Job description

Fiori Technology Solutions is currently hiring for a Design Verification Engineer. This is fulltime permanent position.

We are looking to fill multiple Design Verification openings. We are headquartered in Dallas, USA and have office in Hyderabad, India.

Welcome to a growing team that tests and validates new semiconductor packages. Our exciting IC product lines require thorough and accurate testing to develop detailed wafer maps which identify components that are suitable for production and manufacturing. In this role, you will be a member of a team with an open and collaborative work environment.

Skills and Qualifications Required:

• Roles requiring both 3+ and 8+ years industry experience.
• Bachelor’s or Master’s degree in related engineering field.
• Ability to work independently and across geographies

Specific responsibilities include:

• Digital verification for complex SoC with MCUs (ARM CM0+/CM3/4/CM33) with complex peripherals, hardware accelerators, memory architectures, bus architectures
• Familiar with SoC development flow and environments
• Have experience with mixed signal circuits: ADCs/DACs, OSCs, clock trees, power management circuits together with digital Ips
• Basic understanding of UVM and testcase development in UVM environment
• Working experience with mixed simulation environment (Digital + Analog model)
• Nice to have: Exposure to DPLL/Synthesizer kind of design will make it easier to ramp up.
• Nice to have: Exposure to cadence simulation tools and debugging (simulation, regression, coverage analysis, GLS)

For more information regarding FTS please visit our website https://fiorit.com. We provide an open door policy; please feel free to follow up by email [e-mail] or by phone [phone] and ask for a Talent Manager to assist you.

India Office Plot No 133, Sri Hari Nilayam,
Vaishali Nagar, Madinaguda,
Hyderabad - 500049