AMS Verification Engineer

Optimalsemi; United States; On-site; USD 90,000 - 140,000; Full time

Job summary

FTS Inc is seeking a seasoned verification engineer to support a team of design engineers in validating mixed-signal integrated circuits. You will develop test benches, run regression tests, and work with engineers to resolve bugs while maintaining thorough bug tracking and documentation.

Key tasks include creating verification plans from datasheets, applying stimuli, and upgrading tools and flows with the EDA team.

Qualifications

• Minimum 5+ years of directly related verification experience.
• Experience running simulations and characterizing variance in analog/mixed-signal blocks.
• Pre-silicon verification of mixed-signal products.
• Create verification plans from datasheets and engineer inputs.

Responsibilities

• Develop test benches for mixed-signal IC verification.
• Run regression tests and track results.
• Collaborate with design engineers to reproduce and fix bugs.
• Upgrade tools and flows with the EDA team.
• Review designs to guide verification architecture and features.
• Provide DV status updates to stakeholders.

Skills

5+ years experience

Verilog-AMS

Verilog-A

SystemVerilog

UVM

Python

Perl

Bug tracking

Regression testing

Tools

Cadence Virtuoso

Verilog-AMS

Specman

SystemVerilog

Job description

In this role you will be supporting a team of top-notch Design Engineers providing verification of Mixed Signal Integrated Circuits. You will be developing test benches, conducting regression testing and working with design engineers to resolve any bugs identified. Additionally, you will be responsible for bug tracking and documentation.

What is required to be successful in this opportunity?

• 5+ years directly related experience.
• Run simulations and characterize performance of variance analog blocks and sub-systems
• Execute the pre-silicon verification of mixed-signal products
• Create verification plans using data sheets, inputs from engineers / customers, and working closely with systems engineers
• Implement mixed-signal test-benches in Cadence Virtuoso and/or Verilog-AMS to apply stimulus and checks
• Implement automatic checks and measurements to verify the behavior and populate a Specification Matrix
• Provide periodic updates on DV status to project participants, management, and customers.
• Work with design and systems teams to close bugs as they arise.
• Work with the EDA team to upgrade tools and flows.
• Review the digital and analog design to provide guidance on Mixed Signal Design for Verification architecture and features.
• Verilog and one of Verilog-A or Verilog-AMS or System Verilog or Specman
• Advanced verification methodologies such as UVM
• Bug tracking, functional coverage, RTL code coverage
• Cadence Virtuoso schematic editor
• Strong knowledge in tool and language usage- AMS, Verilog-AMS, System Verilog, PERL or Python
• Capable of Independent interpretation of specification and system
• Strong understanding of circuits and simulation techniques
• Scripting/coding capability with an automation mindset

Applicants must be at least 18 years or older, must be willing to take a drug test and background check as part of the selection process and must have legal authorization to work in India/United States.

FTS Inc does not discriminate in practices or employment opportunities on the basis of an individual's race, color, national or ethnic origin, religion, age, sex, gender, sexual orientation, marital status, veteran status, disability, or any other proscribed category set forth in federal or state regulations.

India Office Plot No 133, Sri Hari Nilayam,
Vaishali Nagar, Madinaguda,
Hyderabad - 500049