Design Verification Engineer

Broadcom; Broomfield (CO); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grant

401(k) participation

Job summary

Broadcom is seeking a Design Verification Engineer to model and verify complex digital and mixed‑signal IP blocks for ASICs. You will define verification plans, build test benches, analyze coverage, and drive debug across RTL and gate‑level contexts.

The role may involve emulation and FPGA prototyping, and adoption of advanced verification methodologies. The candidate should have SystemVerilog, UVM, and experience with assertions, random/directed test cases, and scripting.

Qualifications

• 12+ years of verification experience for digital and mixed-signal circuits.

Responsibilities

• Define verification plans and environment architecture.

Skills

SystemVerilog

UVM

Test benches

Coverage

Perl/Python

Git

EMULATION

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Mentor

Palladium/Veloce/Zebu

Xilinx

Tessent

Job description

USA-CO Broomfield

USA-CA-San Diego-West Bernardo

USA-Colorado-Fort Collins-4380 Ziegler Road

USA-CA San Jose Innovation Drive

USA-CA Irvine Alton Parkway Bldg 1

Full time

R026745

Job Description:

Design Verification Engineer

Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments.

The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debug. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate the block, system, and ASIC level verification. The candidate must work closely with the design teams and EDA vendors to accomplish the modeling and verification tasks.

The candidate must have experience using SystemVerilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random & directed test cases, and SystemVerilog Assertions. This engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate-level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.

Requirements:

• 12+ years of experience with verification concepts and architectures for complex digital and MXS circuits




• Experience verifying designs at the block and system levels.




• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)




• Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / MXS circuits




• Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)




• Experience with Synopsys, Cadence, and Mentor simulations tools




• Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments




• Experience with Perl/Python and Tcl or other scripting languages




• Experience with version control systems (DesignSync, git)




• Superior writing, grammar, and verbal communication skills




• Excellent problem solver; develops and employs automated processes where applicable




• Worked independently and in a global team and dynamic environment in a highly visible role




• Possesses ability to learn and adapt to new tools and methodologies on the fly




• Must have legal authorization to work in the US

It is a plus if the candidate has expertise in one or more of the following areas:

• Experience with hardware design and debug




• Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms




• Formal verification concepts / experience is a plus




• Experience with verifying iJTAG network using ICL and PDL in the Tessent tool a plus




• Experience with co-simulation a plus

Education and Experience required:

• BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom!

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