Design Verification

Apple Inc.; Cupertino (CA); Hybrid; USD 150,000 - 225,000; Full time

Benefits offered by this job

Medical & Dental

Retirement benefits

Employee stock programs

Relocation assistance

Tuition reimbursement

Job summary

Apple Inc. is seeking a hardware verification engineer in Cupertino, CA to verify low power aspects of Apple SOCs. You will develop test plans, create directed and random tests, and write C-based test cases and SystemVerilog models to verify power state transitions.

Collaboration with design, architecture, and software teams is essential, with scripting in Perl/Python to automate regressions. The role offers a competitive base pay and comprehensive Apple benefits, including stock programs,

Qualifications

• Bachelor’s degree in CS/CE or related field plus 2 years of relevant experience.
• Experience with digital/logic design concepts for hardware verification.
• Proficient in ARM/X86 architecture driven verification stimulus.
• C-based stimulus development for chip-level verification.
• SystemVerilog for stimulus and behavioral models.
• C programming for test cases and stimulus.
• Perl or Python for automation and regression maintenance.
• Low-power design fundamentals and UPF power intent.

Responsibilities

• Develop test plans and coverage plans for low power verification of Apple SOCs.
• Create directed and random tests for power manager integration.
• Write tests in C for hardware verification and stimulus.
• Develop SystemVerilog models to simulate SOC with power manager.
• Write scripts (Perl/Python) to automate test execution and regression.
• File bug reports for simulation failures and track until fix.
• Coordinate with design, architecture, software teams to meet project goals.

Skills

Digital design concepts

Logic design

ARM/X86 architecture

C stimulus

SystemVerilog

C programming

Perl/Python scripting

Low power design

UPF power intent

Education

Bachelor’s Degree in CS/CE

Tools

CAD software

AXI/AMBA protocols

Job description

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for low power verification of various Apple SOC. Review power related aspects of design and architecture specifications of SOCs and corresponding Power Manager SOCs and work closely with design, architecture, software teams to identify attributes that need to be tested. Develop test plan and coverage plans and develop, define test benches needed for executing on the test plan. Develop specific test plans to verify low power functionality of various system on chip designs. Develop specific test plans to verify hardware within system on chip responsible for restoring hardware to correct state as chip goes through power state transitions. Create directed and random tests for testing the integration of power manager. Write tests in C programming language for testing the hardware. Create system Verilog behavioral models and stimulus to test the simulation of system on chip with power manager chip together. Write scripts in Perl and Python programming languages to automate the verification of test plan. Create scripts and regressions to track and maintain chip simulations. Run chip level simulations using CAD software. Use AXI,AMBA Protocols to verify integration of various blocks within chip and debug failing test cases. File bug reports for simulation failures and track them until fix and closure. Work independently and manage deliverables to align with project goals and support cross functional engineering efforts.40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Bachelor’s Degree or foreign equivalent in Computer Science, Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
• 2 years of experience with each of the following skills is required:
• Using digital and logic design concepts to understand the process of hardware design and verification
• Utilizing ARM/X86 based Computer architecture to drive processor-based verification stimulus
• Using data structures and algorithms to write efficient C based stimulus for chip level verification
• Utilizing System Verilog to create stimulus and behavioral models to validate chip design systems
• Using C to write chip level test cases that drive stimulus
• Utilizing Perl or Python to automate tasks like running testcases, failure triaging and regression maintenance.
• Utilizing low power design fundamentals specific to CMOS based designs.
• Using languages including UPF to describe power intent for hardware designs

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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