Physical Design Engineer

Apple Inc.; Cupertino (CA); Hybrid; USD 174.000 - 225.000; Vollzeit

Zusammenfassung

Apple Inc. in Cupertino, California, is seeking a Senior IC Design Engineer to lead power reduction and physical design for advanced node SoCs.

You will perform static and dynamic power analysis, implement low power techniques, fix violations, and drive tape-out readiness with partitioning, floorplanning, and ECOs. You will develop CAD tool flows, script in TCL/Perl/Python, collaborate with logic design, and push design closure through sign-off for timing, PDV, and reliability.

Qualifikationen

• Master's degree or foreign equivalent in Computer Engineering or related field.
• 3 years of experience in the job offered or related occupation.
• Utilize Innovus or Fusion Compiler APR tools to perform implementation design and support execution of tasks.
• Tune implementation design flows and methodologies to improve power, performance, and area.
• Perform static timing analysis and apply timing convergence techniques; debug LVC/DRC violations.
• Perform physical design on advanced technology nodes (7nm and below) with CMOS fabrication knowledge.
• Perform block level physical design, including floor planning, placement, clock tree synthesis, routing, and ECO steps.
• Utilize lower power design techniques including clock gating, power gating, and multi-voltage domains.

Aufgaben

• Analyze and perform static and dynamic power reduction of advanced SoC designs; meet power target goals.
• Implement low power techniques and complete ECOs to fix identified design violations.
• Develop CAD tool flows and automation for design efficiency.
• Execute chip/partition floor planning, pin assignment, macro placement, and evaluate logic placement to improve power, performance, and area.
• Work with the logic design team to align partition architecture with early physical design considerations; drive signoff closure for partitions.

Jobbeschreibung

Cupertino, California, United States Hardware

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Analyze and perform static and dynamic power reduction of the advanced node technology and complex SoC design. Implement the low power design techniques and meet the power target goals. Perform critical ECOs (Engineering Change Orders) to fix the identified violations from the analysis of all design aspects, such as Timing, Physical verification, Power Grid integrity, and Logic equivalent checks for design closure for tape out. Perform scripting and programming for CAD tool flow development for automation problem solving and efficiency improvement. Execute chip/partition floor planning, pin assignment, macro placement, and evaluation of logic placement to improve design power, performance and area. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical and electrical verification and driving the signoff closure for the partitions. Resolve and improving design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master's degree or foreign equivalent in Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
• Experience and/or education must include:
• 1. Utilize Innovus or Fusion Compiler APR tools to perform implementation design, including applying these tools in physical design workflows and supporting execution of implementation design tasks.
• 2. Tune implementation design flows and methodologies to improve the power, performance, and area of designs.
• 3. Perform static timing analysis and apply timing convergence techniques, conduct IR/IVD analysis, implement violation fixes, and debug and resolve LVC/DRC violations.
• 4. Perform physical design on advanced technology nodes (7nm and below), with knowledge of modern CMOS technology and fabrication fundamentals.
• 5. Perform block level physical design, including floor planning, placement, clock tree synthesis, routing, and ECO step implementation.
• 6. Utilize lower power design techniques, including clock gating, power gating, and multi-voltage domain design.
• 7. Utilize scripting language, TCL, Perl, or Python to implement automatic techniques.
• 8. Apply top down and bottom up design approaches and resolve interblock design issues related to timing and PDV related issues.

Preferred Qualifications

• N/A

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