Design Lead

HCLTech; San Diego (CA); On-site; USD 110,000 - 150,000; Full time

Job summary

HCL Technologies Limited is seeking a Design Lead for the San Diego location to join the Hardware Test Engineering (HWTE) group. The role focuses on SMT test station design, DFT, and cross-functional collaboration to ensure robust test capabilities from EVT to PVT.

Strong electronics design and testing experience is required. The candidate will work closely with cross-functional teams, contribute to post-build reviews, and help drive test coverage and reliability of the hardware platform.

Qualifications

• B.Sc. in EE with 3+ years or M.Sc. in EE with 1+ year experience.
• Strong analog, digital and power electronics hardware knowledge.
• Schematic & PCB layout design using Allegro or similar CAD tool.
• Design and debug complex electrical schematics and PCB layouts.
• Familiar with USB 3.2, USB-PD, DisplayPort, PCIe, I2C, SPI protocols.

Responsibilities

• Assist in product DFT and test point coverage analysis.
• Design SMT test stations with signal conditioning and FMEA.
• Review post-mortem results after builds with the Ops team.
• Support EVT/POC/DVT phases and ensure project handover success.

Education

B.Sc. in EE

M.Sc. in EE

Tools

Allegro CAD

Job description

Career Opportunities: Design Lead (190562)

Requisition ID190562-Posted11/06/2026

Client’s Hardware Test Engineering (HWTE) group is looking for a passionate, highly collaborative

vendor for supporting SMT HW managed service. In this engagement, vendor need to provide

SMT Engineering Service Support for Hardware Test, SW, and Program Management. Home/VPG/Accys NPI testing (San Diego position)

Key Responsibilities

• Assist in product DFT (DUT design check, test point presence check, test coverage analysis).

Accordingly, design SMT test stations (interface board with signal conditioning circuit, performdesign FMEA). The design shall pass all FBU (fixture bringup checklist) criteria and meet alltest coverage requirements without any gaps.

• During POC, EVT, DVT, we will setup Post mortem after each build to review if the build eventwas adequately supported.
• After the project is handed over to Ops Team at PVT, we will review the entire projects and gather the lesson learn for each project.
• If there is no red flag or issues / concerns highlighted by TDL, then this project is successfullysupported.

Skill Requirements

• B.Sc. in EE with 3+ years of experience or M.Sc. in EE + 1 years of relevant experience
• Good understanding analog, digital, and power electronics hardware architectures and design
• Experience in schematic & PCB layout design using Allegro or a similar CAD tool
• Ability to design and debug complex electrical schematics and PCB layouts and propose clear,relevant experiments
• Working knowledge of USB 3.2, USB-PD, Display Port, PCIe, I2C, SPI technologies andprotocols, and design
• Good oral & written communication skills - be able to communicate complex engineeringconcepts clearly and concisely to various cross functional teams and leadership.

Other Requirements

• Prior experience with bed of nails test fixture and designing custom test instruments
• Prior experience of performing parametric data statistical analysis (CPK, GRR etc)
• Prior technical leadership and/or project management experience