Design Implementation Engineer (Synthesis / STA)

Broadcom, Inc.; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company matching

ESPP - Employee Stock Purchase Program

EAP - Employee Assistance Program

Paid holidays

Sick leave and vacation

Paid family leave

Job summary

Broadcom, Inc. is seeking a senior ASIC engineer to lead synthesis, STA, and formal verification for complex Mixed Signal blocks. The role includes timing signoff, ECO-driven closure, and ownership of IP releases, ensuring integrity before handoff to customers or SoC teams.

You'll implement automation tools, work with Design Compiler, Genus, PrimeTime, and Calibre/Icc2/Innovus, and collaborate across global design and physical teams on advanced technology nodes.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or a related field with 8+ years of related experience, OR an MS with 6+ years of related experience.
• Experience with high-complexity silicon in advanced technology nodes is required.
• Hands-on experience with hardware data management tools (Git, DesignSync) for IP releases.
• Strong familiarity with UPF/CPF low-power design methodologies.
• Automation via scripting (Tcl, Python/Perl) and AI-assisted tooling is a plus.

Responsibilities

• Lead synthesis and low-power implementation for digital/mixed-signal blocks.
• Manage timing constraints, STA, and timing signoff methodologies with corners and derating.
• Run Formal Verification and LEC to ensure functional correctness across design flow.
• Drive timing closure with ECOs and QoR evaluation pre/post-route.
• Serve as IP Release Owner, auditing files and ensuring proper tagging before handoff.
• Develop automation scripts to streamline implementation and audit tasks.

Skills

Synthesis

STA

Formal verification

Low-power audits

Automation scripting

Git

DesignSync

IP release

Education

BS in Electrical Engineering/Computer Engineering

MS with 6+ years

Tools

Design Compiler

Genus

PrimeTime

Tempus

Formality

VCLP

ICC2

Calibre

Innovus

Job description

USA-CO Broomfield

USA-Colorado-Fort Collins-4380 Ziegler Road

USA-CA San Jose Innovation Drive

USA-CA Irvine Alton Parkway Bldg 1

Full time

R027646

Job Description:

The candidate will be responsible for leading and executing Synthesis, Static Timing Analysis (STA), Formal Verification, and low-power implementation activities of Mixed Signal (MXS) blocks. Additionally, this role acts as the IP Release Owner, managing the critical integrity checks prior to IP block handoff to consumers. You will utilize advanced automation and modern engineering workflows to drive functional, physical, and deployment readiness for complex ASIC blocks in advanced technology nodes.

Responsibilities Include:

• Synthesis & Low-Power Implementation: Execute synthesis and run static checks (CDC, RDC, UPF/CPF power intent) for digital/mixed-signal blocks.
• Timing & Constraint Management: Create, validate, and maintain timing constraints. Perform STA and define timing signoff methodologies, including corners and derating.
• Formal Verification: Run Formal Verification and logical equivalence checking (LEC) throughout the design flow to guarantee functional correctness.
• Timing Closure: Generate and implement timing/functional ECOs to drive timing closure, evaluating pre- and post-route Quality of Results (QoR).
• IP Release Ownership: Serve as the final gatekeeper for IP deployment by driving the release validation flow, auditing files for synchronization gaps, and ensuring proper tagging via revision control utilities before handing off to customers or SoC teams.
• Workflow Automation: Build and deploy custom script-based automation to streamline implementation and audit tasks.

Qualifications:

• Extensive experience with high-complexity silicon in advanced technology nodes.
• Expertise in industry-standard tools for synthesis, STA, formal verification, and low-power audits (e.g., Design Compiler, Genus, PrimeTime, Tempus, Formality, VCLP).
• Hands-on experience with hardware data management tools (e.g., Git, DesignSync or equivalent) for managing complex, hierarchical IP releases.
• Strong familiarity with UPF/CPF low-power design methodologies.
• Automation & Modern Tooling: Experience developing custom automation tools using scripting languages (Tcl, Perl/Python) to optimize daily workloads, alongside experience leveraging AI code-assist tools to accelerate script generation/code debug.
• Strong analytical mindset, excellent problem-solving skills, and acute attention to detail.
• Effective communication skills to act as a cross-functional liaison between global design and physical implementation teams.
• Direct experience with physical design implementation steps, including partitioning, floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC using tools like Calibre, ICC2, or Innovus) is a plus.
• Direct or indirect experience with RTL design and architecture is a plus.
• Contributed to the successful tapeout or release deployment of at least 1–2 high-complexity ASICs/SoCs.

Education and Experience Required:

• BS in Electrical Engineering, Computer Engineering, or a related field with 8+ years of related experience, OR an MS with 6+ years of related experience.

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom!

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

For more information please visit our video library (http://www.broadcom.com/videos) and check out our Connected by Broadcom (https://www.broadcom.com/support/resources/video-webinar-library?channel=5c9658f7c1d34eca91c6cc16178e5b1b&video=7d72b04ea50046a394e682fab640ce20) series.

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