Design Engineer I - Modem Design

Silicon Laboratories Inc.; Austin (TX); On-site; USD 78,750 - 146,250; Full time

Benefits offered by this job

Health plan options

401k plan with match

Flexible PTO schedule

Tuition reimbursement

Onsite gym

Free snacks

Job summary

Silicon Laboratories Inc. in Austin, Texas, is looking for an experienced engineer to join the PHYMAC MODEM team. The role involves designing and verifying digital components for low-power wireless products, requiring expertise in RTL design and digital verification methodologies.

The ideal candidate will have a strong academic background in Electrical Engineering and practical skills in tools such as Verilog, SystemVerilog, and MATLAB. The company offers a competitive compensation package along with comprehensive benefits.

Qualifications

• Experience with RTL design and verification.
• Understanding of synchronous design and state machines.
• Ability to document design decisions and present technical findings.

Responsibilities

• Design digital blocks for low‑power wireless products.
• Collaborate with teams to translate requirements into digital architectures.
• Contribute to integration and validation of designs.

Skills

Digital design fundamentals

RTL design using Verilog/SystemVerilog

Basic programming skills in Python or MATLAB

Debugging and verification methodologies

Knowledge of DSP concepts

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or related field

Tools

Questa tools

MATLAB

Job description

Silicon Labs is a leading innovator in low‑power wireless connectivity, building embedded technology that connects devices and improves lives. You’ll join the PHYMAC MODEM team, which designs digital components of Silicon Labs’ low‑power wireless products.

Responsibilities

• Design, model, and verify digital blocks for low‑power wireless products.
• Develop RTL implementations and verification environments to ensure functionality, performance, and quality.
• Collaborate with cross‑functional teams to translate wireless system requirements into efficient digital architectures and implementations.
• Debug and resolve design and verification issues throughout the development cycle.
• Contribute to the integration, bring‑up, and validation of digital modules within larger system‑on‑chip (SoC) designs.
• Develop scripts and tools to improve design, verification, and testing efficiency.
• Document design decisions, verification results, and technical findings, and present work to the broader engineering team.

Minimum Qualifications

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with RTL design using Verilog and/or SystemVerilog.
• Experience with digital design simulation and verification methodologies and tools.
• Understanding of digital design fundamentals, including synchronous design, state machines, timing, and logic optimization.
• Basic programming skills in Python, MATLAB, or a similar language for automation, testing, or data analysis.

Preferred Qualifications

• Knowledge of Digital Signal Processing (DSP) concepts and digital communications systems.
• Experience with MATLAB modeling for DSP and wireless communication algorithms.
• RTL design and verification experience using Verilog/SystemVerilog and Questa tools.
• Familiarity with wireless communication standards such as Bluetooth Low Energy, Zigbee, Thread, Wi‑Fi, or proprietary wireless protocols.
• Experience with FPGA development, hardware bring‑up, or lab‑based debugging.
• Exposure to ASIC or SoC design flows, including synthesis, linting, CDC analysis, or formal verification.

Benefits & Perks

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA)
• Dental and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back‑Up childcare
• Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
• Flexible PTO schedule
• 3 paid volunteer days per year
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO

Compensation

The annualized base pay range for this role is expected to be between $78,750 – $146,250 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed, and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

Equal Opportunity Employment

Silicon Labs is an equal opportunity employer and values the diversity of its employees. Employment decisions are made on the basis of qualifications and job‑related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by applicable law.