Design Engineer

Acceler8 Talent; Berkeley (CA); On-site; USD 162,000 - 198,000; Full time

Benefits offered by this job

Medical insurance

Vision insurance

401(k)

Dental insurance

Job summary

Acceler8 Talent is seeking a Digital IC Design Engineer to join an early-stage photonic computing company in Berkeley. The role covers RTL through tape-out, with hands-on work across RTL design, synthesis, place-and-route and silicon bring-up in a fast-paced startup environment.

This onsite position offers base salary from $180,000 plus equity and visa sponsorship. You will collaborate across architecture, design and verification teams to build a new computing platform for AI workloads.

Qualifications

• Strong RTL experience with Verilog or SystemVerilog.
• Hands-on synthesis, timing analysis and physical implementation.
• Experience delivering a chip or large digital block to lab testing.

Responsibilities

• Design and integrate RTL for digital functions and interfaces (UART, SPI, SRAM).
• Run synthesis, static timing analysis, gate-level sim, and place-and-route.
• Work with process tech, standard-cell libs and physical constraints.
• Support tape-out, lab bring-up and post-silicon validation.
• Collaborate across architecture, design, verification and implementation.

Skills

RTL design

Verilog/SystemVerilog

Synthesis

Timing analysis

Physical implementation

Lab bring-up

Chip tape-out

Job description

Hiring: Digital IC Design Engineer

Location: Berkeley, California

Working model: Onsite, five days per week

Compensation: From $180,000 base salary, plus equity

Visa sponsorship: Available

We are hiring a Digital IC Design Engineer to join an early-stage photonic computing company building a new hardware platform for AI workloads. This is a broad, hands-on role for someone who wants to take digital blocks from RTL design through synthesis, physical implementation, tape-out and silicon bring-up.

What you will own

• Design and integrate RTL for digital functions and interfaces, including UART, SPI and SRAM connectivity.
• Run synthesis, static timing analysis, gate-level simulation and place-and-route flows.
• Work with advanced process technologies, standard-cell libraries and physical-design constraints.
• Support chip tape-out, lab bring-up and post-silicon validation.
• Work across architecture, design, verification and implementation as needed.
• Help build the company’s wider digital IC capability as the team grows.

What we are looking for

• Strong RTL experience using Verilog or SystemVerilog.
• Hands-on exposure to synthesis, timing analysis and physical implementation.
• Experience taking a chip or substantial digital block through implementation and into the lab.
• Comfort working across multiple stages of the digital design flow.
• A resourceful, ownership-driven approach suited to an early-stage startup.

Why join?

This is an opportunity to own meaningful parts of a chip, work across photonic ICs, electronic ICs, packaging and architecture, and help shape a new computing platform from an early stage.

Featured benefits

• Medical insurance
• Vision insurance
• 401(k)
• Dental insurance