Cryogenic RFIC Design Engineer for Quantum Systems

Global Foundries; Austin (TX); On-site; USD 98,000 - 202,000; Full time

Job summary

GlobalFoundries in the United States (Austin, TX) invites an experienced Senior RF IC Design Engineer to develop high-performance RF/microwave ICs and reusable IP, spanning architecture to tapeout and silicon characterization.

You will collaborate with technology, PDK, modeling, packaging, and test teams to optimize designs for cryogenic CMOS and quantum applications, while mentoring junior engineers.

Qualifications

• Bachelor's degree in Electrical Engineering, Microelectronics, Applied Physics or related field.
• Minimum 5 years of RF, microwave, or analog IC design experience.
• Experience taking RFIC through schematic, layout, tapeout and silicon validation.

Responsibilities

• Design and develop RF/microwave ICs and reusable IP including LNAs, PAs, mixers, VCOs and PLLs.
• Lead architecture-to-layout RFIC development with tapeout and silicon validation.
• Perform RF circuit analysis including S-parameters, noise figure, gain, stability, phase noise and impedance matching.
• Do electromagnetic simulation and modeling of passive RF structures and interconnects.
• Collaborate with modeling, PDK, technology, packaging and test teams to ensure model accuracy.
• Lead design reviews, document methodology, and mentor engineers.

Skills

RFIC design

Schematic design

Layout and DRC/LVS

Parasitic extraction

Tapeout

Silicon validation

Impedance matching

S-parameters

Phase noise

Noise figure

RF measurement concepts

Education

Bachelor's degree in Electrical Engineering, Microelectronics, Applied Physics

Master's degree or PhD in Electrical Engineering, Microelectronics, RF/Microwave Engineering

Job description

GlobalFoundries in the United States (Austin, TX) invites an experienced Senior RF IC Design Engineer to develop high-performance RF/microwave ICs and reusable IP, spanning architecture to tapeout and silicon characterization.

You will collaborate with technology, PDK, modeling, packaging, and test teams to optimize designs for cryogenic CMOS and quantum applications, while mentoring junior engineers.