Cryogenic CMOS Digital IC Architect

GlobalFoundries; Santa Clara (CA); On-site; USD 98,000 - 202,000; Full time

Job summary

GlobalFoundries is seeking a Senior Digital IC Design Engineer to develop digital and mixed-signal IP for cryogenic CMOS and quantum systems. You will drive designs from architecture and RTL through physical implementation, tapeout, and silicon validation while collaborating with technology, PDK, modeling, verification, and test teams.

Responsibilities include design of digital CMOS circuits, ownership of IC development, verification strategy development, and post-layout signoff.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related field.
• Minimum 5 years of relevant digital IC/ASIC design experience.
• Experience with RTL design and verification using Verilog, SystemVerilog, VHDL, or equivalents.
• Experience with ASIC design flows including synthesis, STA, clock/reset methodology, DFT/scan, physical implementation, timing closure, and signoff.
• Strong understanding of synchronous digital design, CDC, RDC, low-power design concepts, and PVT-related timing behavior.
• Proficiency with industry-standard digital design, verification, implementation, and analysis tools and the ability to debug complex pre-silicon and silicon issues.
• Travel up to 10%.
• Fluency in English (written & verbal).

Responsibilities

• Design and develop digital CMOS circuits, digital subsystems, and reusable IP for advanced semiconductor applications.
• Own digital IC development from microarchitecture and RTL implementation through verification, synthesis, timing closure, physical implementation, tapeout, and silicon validation.
• Develop and execute verification strategies using simulation, assertions, coverage, and regression methodologies.
• Perform and support synthesis, static timing analysis, clock/reset design, power analysis, DFT/scan, and physical implementation activities, including post-layout verification and design signoff.
• Optimize digital architectures for power, performance, area, reliability, and operating-temperature requirements, including cryogenic conditions where applicable.
• Collaborate with PDK, device modeling, technology, analog, layout, and EDA teams to evaluate design methodology and implementation flows for emerging technologies.
• Define silicon test and characterization requirements, analyze measured data, debug timing issues, and correlate silicon with pre-silicon models.
• Lead technical design reviews, document methodology, mentor engineers, and collaborate with cross-functional teams to enable solutions.

Skills

RTL design & verification

Verilog/SystemVerilog/VHDL

Synchronous digital design

Clock-domain crossing

Low-power design

Timing closure/STA

Pre-silicon/silicon debugging

Education

Bachelor’s degree in Electrical/Computer Engineering

Tools

RTL design tools

Static timing analysis tools

DFT/Scan tools

EDA tool suites

Job description

GlobalFoundries is seeking a Senior Digital IC Design Engineer to develop digital and mixed-signal IP for cryogenic CMOS and quantum systems. You will drive designs from architecture and RTL through physical implementation, tapeout, and silicon validation while collaborating with technology, PDK, modeling, verification, and test teams.

Responsibilities include design of digital CMOS circuits, ownership of IC development, verification strategy development, and post-layout signoff.