CPU Verification Engineer: Cache & AI-Driven Validation

Advanced Micro Devices; Fort Collins (CO); On-site; USD 110,000 - 160,000; Full time

Job summary

Advanced Micro Devices in Fort Collins, Colorado is seeking an experienced verification engineer to join the Cores organization and verify cache subsystems in high-performance processors.

You will build and maintain C++ verification environments, develop test programs in C and assembly, and collaborate with RTL design, architecture, and physical design teams to ensure thorough validation from block level to full-chip integration.

Qualifications

• Strong C++ programming skills and a solid understanding of computer architecture.
• Experience performing functional verification on CPU, GPU, or ASIC/SoC designs.
• Proficiency in Python or Perl scripting for test automation.
• Familiarity with RTL simulation and debugging tools.

Responsibilities

• Perform functional verification of L2 and L3 cache subsystems at block and full-chip levels.
• Build and maintain C++ verification environments including reference models, checkers, and scoreboards.
• Develop C and assembly test programs to validate cache behavior and expose corner cases.
• Debug failing tests to root cause and work with design engineers to drive resolution.
• Develop test plans and contribute to coverage closure.
• Apply AI-assisted tools and workflows as part of an innovative, modern verification practice.

Skills

C++ programming

Python scripting

Problem solving

Education

Bachelor's/Master's in Electrical/Computer Engineering or Computer Science

Master's degree preferred

Tools

RTL simulation tools

Debug tools

Verification infrastructure

Job description

Advanced Micro Devices in Fort Collins, Colorado is seeking an experienced verification engineer to join the Cores organization and verify cache subsystems in high-performance processors.

You will build and maintain C++ verification environments, develop test programs in C and assembly, and collaborate with RTL design, architecture, and physical design teams to ensure thorough validation from block level to full-chip integration.