CPU RTL Automation Engineer

MaC VC; Austin (TX); On-site; USD 209,000 - 314,000; Full time

Job summary

Qualcomm Technologies, Inc. in Austin, TX is seeking a seasoned engineer blending RTL design and CAD automation to support CPU development. You will build scalable tooling and scripts to streamline design, debug, and verification workflows.

You will work with CPU design teams, triage RTL issues, maintain RTL databases with Git, and contribute to CI/CD pipelines. Proficiency in Verilog/SystemVerilog, Python, and CAD tools is required; advanced scripting is a plus.

Qualifications

• Experience in RTL design and CPU microarchitecture.
• Knowledge of RTL databases and Git version control.
• Ability to triage RTL issues and support design/debug workflows.
• Advanced Python scripting; familiarity with TCL/Perl/Bash is a plus.

Responsibilities

• Define and develop methodologies to build scalable CPU designs.
• Support RTL development and debug workflows across CPU design teams.
• Maintain and enhance RTL databases and repositories using Git.
• Triage RTL issues and collaborate with design teams to resolve them.
• Develop and maintain automation scripts and tools in Python to improve RTL workflows.
• Interface with CAD teams to align RTL tooling with design infrastructure.
• Contribute to CI/CD pipelines and build systems for RTL environments.
• Document workflows, tools, and best practices for internal teams.

Skills

RTL design

CPU microarchitecture

Git (version control)

Python scripting

Problem solving

Communication

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree in Electrical/Computer Engineering or related field

PhD in Electrical/Computer Engineering or related field

Tools

Python

Git

CAD tools

TCL

Perl

Bash

Job description

Qualcomm Technologies, Inc. in Austin, TX is seeking a seasoned engineer blending RTL design and CAD automation to support CPU development. You will build scalable tooling and scripts to streamline design, debug, and verification workflows.

You will work with CPU design teams, triage RTL issues, maintain RTL databases with Git, and contribute to CI/CD pipelines. Proficiency in Verilog/SystemVerilog, Python, and CAD tools is required; advanced scripting is a plus.