CPU Implementation Feasibility Engineer

Socket.dev; Austin (TX); On-site; USD 150,000 - 200,000; Full time

Job summary

Apple's Silicon Engineering Group in Austin seeks an experienced CPU design engineer to join the RTL feasibility team. You will help translate ambitious microarchitectural ideas into buildable, high-performance, low-power silicon through RTL work and close collaboration with RTL, physical design, and verification teams.

Responsibilities include feasibility experiments, area, frequency, power trade-offs, and driving RTL-to-GDS flows with aggressive targets for timing and power.

Qualifications

• BS degree with 3+ years in a related field.
• Experience with high-performance VLSI implementations.
• Experience with CPU microarchitecture is required.

Responsibilities

• Perform feasibility experiments for RTL innovations and improvements.
• Evaluate area, frequency, performance and power trade-offs.
• Drive RTL-to-GDS flow with aggressive goals for power, performance and area.
• Collaborate with multi-functional teams to validate physical design aspects.
• Conduct floor planning experiments to assess microarchitectural feasibility.

Skills

VLSI implementation

CPU microarchitecture

Industry experience

Education

BS degree

Tools

LEC tools

Static Timing Analysis Tools

Power analysis tools

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring your passion and dedication, and there's no telling what you could accomplish. Here, dynamic people and innovative technologies are the norm — the engineers on our teams have reinvented entire industries through Apple hardware. That same drive for innovation extends to how we work, and to our commitment to leave the world better than we found it. Apple's Silicon Engineering Group (SEG) is looking for talented engineers to join our CPU implementation feasibility team. You'll help shape the next generation of Apple silicon from the earliest stages, working with RTL on turning ambitious microarchitectural ideas into buildable, high-performance, low-power designs.

Description

Responsibilities also include but are not limited to:

• Performing different feasibility experiments for RTL innovations and improvements that drive the next generation high performance and low power chips
• Making area, frequency, performance and power trade-offs
• Driving RTL-to-GDS flow through synthesis/place-and-route with ambitious goals for power, performance, and area
• Working with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, power, testability, and reliability
• Performing different floor planning experiments to understand the microarchitectural feasibility for achieving high targets for performance, power and area

Minimum Qualifications

• Minimum BS and 3+ years of relevant industry experience
• Experience with VLSI implementation on high performance designs
• Experience with CPU microarchitecture

Preferred Qualifications

• Understanding of static timing analysis and power
• Physical Design Fundamentals
• Implementation experience on high performance CPU designs
• Experience with Logical Equivalence checking (LEC) tools
• Experience with Power analysis tools
• Experience with Static Timing Analysis Tools
• Understanding of power, performance and area tradeoffs
• Strong communication