Coherent Interconnect RTL Design Engineer

Arm; Austin (TX); Hybrid; USD 161,500 - 218,500; Full time

Job summary

Arm in Austin seeks an RTL logic design engineer to join the System IP Coherent Interconnect team. You will work on scalable, configurable mesh IP delivering high bandwidth with power efficiency for AI infrastructure, IoT, and automotive markets.

You will collaborate with verification, implementation, performance, and project management to ensure on-time delivery of high-quality designs, using SystemVerilog, with awareness of PPA trade-offs and low-power techniques.

Qualifications

• Experience in fabric and interconnect design
• Knowledge of high-speed interfaces such as AMBA CHI and/or AXI
• Familiarity with PCI Express, Ethernet, DDR is a plus
• Minimum Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Responsibilities

• Logic design using SystemVerilog RTL coding
• Plan, track, and coordinate tasks to meet milestones
• Collaborate with design, tool, verification, and power teams to deliver high-quality hardware designs
• Improve design methodology across the System IP group and wider Arm design community

Skills

SystemVerilog RTL coding

High-speed interfaces

AMBA CHI/AXI

PCIe/Ethernet/DDR

Bachelor/Master in CE/EE

Education

Bachelors or Masters in Computer/Electrical Engineering

Job description

Arm in Austin seeks an RTL logic design engineer to join the System IP Coherent Interconnect team. You will work on scalable, configurable mesh IP delivering high bandwidth with power efficiency for AI infrastructure, IoT, and automotive markets.

You will collaborate with verification, implementation, performance, and project management to ensure on-time delivery of high-quality designs, using SystemVerilog, with awareness of PPA trade-offs and low-power techniques.