CMOS Device Integration Leader for Next‑Gen Memory

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Paid holidays

Job summary

Micron Technology in Boise, Idaho seeks a Distinguished Member of Technical Staff to lead CMOS device integration for next-generation DRAM and memory architectures. The role requires coordinating across Design, TCAD, Modeling, Process, Reliability, and Layout teams to deliver integrated technology solutions.

The candidate will provide technical leadership, strategic recommendations, and clear presentations to guide technology direction.

Qualifications

• Master’s degree or PhD in Electrical Engineering or equivalent practical experience.
• Experience leading and coordinating complex, cross-functional technology development projects.
• Hands-on experience in advanced CMOS device design and/or integration.
• Semiconductor industry experience at a leading logic foundry or DRAM manufacturer.

Responsibilities

• Develop and integrate advanced CMOS devices for next-generation DRAM and memory architectures.
• Perform detailed electrical characterization of CMOS devices and circuits to drive performance improvements.
• Partner with Design, TCAD, Modeling, Process, Reliability, and Layout teams to deliver integrated technology solutions.
• Provide technical leadership, strategic recommendations, and clear presentations to guide technology direction.

Skills

Leadership

Cross-functional

CMOS device design

Device integration

Education

Master’s degree in Electrical Engineering

PhD in Electrical Engineering

Job description

Micron Technology in Boise, Idaho seeks a Distinguished Member of Technical Staff to lead CMOS device integration for next-generation DRAM and memory architectures. The role requires coordinating across Design, TCAD, Modeling, Process, Reliability, and Layout teams to deliver integrated technology solutions.

The candidate will provide technical leadership, strategic recommendations, and clear presentations to guide technology direction.