Clocking Architect

191 Altera Corporation; San Jose (CA); Hybrid; USD 187,000 - 270,700; Full time

Benefits offered by this job

Medical, dental, and vision coverage

401(k) with company match

Paid parental leave

Flexible hybrid work model

Professional development investment

Job summary

191 Altera Corporation is searching for a skilled FPGA Clocking Architect to lead clocking architecture for its FPGA/SoC devices. You will drive clocking solutions for advanced digital interfaces and ensure compliance with power budgets and timing constraints.

The ideal candidate has over 12 years of experience in physical design and a strong background in clocking architectures. Benefits include medical coverage, a 401(k) plan, and a flexible hybrid work model.

Qualifications

• 12+ years of experience in physical design, SoC/FPGA design, or clocking architecture.
• Proven ownership of full chip and subsystem-level clocking architecture.
• Expert-level CDC architecture ownership, including synchronizer strategy and metastability analysis.

Responsibilities

• Lead the end-to-end clocking architecture for Altera’s FPGA/SoC devices.
• Define subsystem-level clocking plans and establish clock gating techniques.
• Develop protocol-specific clocking solutions for various digital interfaces.

Skills

Clocking architecture

Physical design

SoC/FPGA design

CDC verification tools

Low-power design methodologies

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

PrimeTime

Tempus

SpyGlass CDC

JasperGold CDC

Questa CDC

Job description

About Altera

Altera is a leading FPGA solutions provider focused on delivering programmable technologies for AI, cloud, networking, and edge markets.

Key Responsibilities

• Lead the end‑to‑end clocking architecture for Altera’s FPGA/SoC devices, including clock tree topology, domain partitioning, frequency planning, and PLL/DLL resource allocation.
• Define subsystem‑level clocking plans aligned with chip‑level power budgets, protocol timing margins, and physical implementation constraints; establish clock gating, low‑power techniques, and dynamic frequency scaling strategies.
• Develop protocol‑specific clocking solutions for PCIe, high‑speed memory interfaces (DDR5, LPDDR5, HBM), ARM subsystems, configuration interfaces, Ethernet, and SerDes.
• Architect clocking for ML/AI accelerator pipelines, including multi‑frequency compute, memory, and interconnect planes, DVFS, and high‑bandwidth memory interfaces.
• Own the full‑chip CDC architecture, including synchronizer strategies, metastability analysis, and end‑to‑end CDC sign‑off; drive CDC verification using industry tools and establish coding guidelines.
• Author SDC constraints for functional timing, DFT modes (scan, ATPG, MBIST, LBIST), and manage OCC strategies for scan clock control.
• Collaborate with RTL, physical design, timing, and verification teams; lead clocking architecture reviews with IP owners, SoC architects, and external vendors; mentor junior engineers and represent the clocking team in design reviews and customer engagements.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12+ years of experience in physical design, SoC/FPGA design, or clocking architecture, with silicon tape‑outs at 7nm or below.
• Proven ownership of full‑chip and subsystem‑level clocking architecture on high‑complexity SoC or FPGA devices.
• Deep expertise in PCIe (Gen4/5/6), DDR5/LPDDR5/HBM, ARM CoreLink/CMN, Ethernet (1G–400G), configuration interfaces, and SerDes clocking.
• Experience architecting clocking for ML/AI accelerator silicon, including multi‑frequency planes, DVFS, and HBM/LPDDR5X integration.
• Expert‑level CDC architecture ownership: full‑chip planning, synchronizer strategy, metastability analysis, and sign‑off.
• Proficiency with CDC verification tools (SpyGlass CDC, JasperGold CDC, Questa CDC) and SDC constraint authoring using PrimeTime and/or Tempus.
• Comprehensive DFT clocking experience: scan, ATPG, OCC, MBIST, LBIST, and associated SDC methodology.
• Knowledge of low‑power design methodologies (UPF/CPF) and their interaction with clock gating and multi‑voltage domains.
• Preferred: FPGA background with understanding of PLLs, global/regional clock networks, GCLK/RCLK routing; experience with FPGA hard IP subsystems; scripting proficiency in Tcl or Python for constraint automation.
• Applicants must be eligible for any required U.S. export authorizations.

Benefits

• Medical, dental, and vision coverage
• 401(k) with company match
• Paid parental leave
• Flexible hybrid work model and dedicated professional development investment
• Access to Altera’s world‑class EDA infrastructure, IP libraries, and advanced process node programs

Salary Range: $187,000 - $270,700 USD (BayArea, California)

Job Type: Regular

Shift: Shift1 (United States of America)

Primary Location: SanJose, California, United States

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.