Chip Lead: End-to-End SoC Architect & Debug Champion

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 232,000 - 368,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA is hiring a Chip Lead to serve as the technical lead for a major silicon program. You will be the primary technical partner across design, validation, software, and manufacturing, accountable for the chip's end-to-end technical integrity and for guiding multi-functional decisions.

The role demands >15 years in post-silicon bring-up, validation, or system integration within a major semiconductor company, with deep expertise in SoC/ASIC architecture and

Qualifications

• BS or MS in Electrical or Computer Engineering (or equivalent).
• 15+ years of post-silicon bring-up, validation, or system integration leadership.
• End-to-end understanding of SoC/ASIC architecture with cross-functional impact.
• Proven ability to guide technical decisions across teams without direct reports.

Responsibilities

• Serve as single technical point of contact for multi-functional decisions and trade-offs.
• Co-lead feature integration from chip to system and surface inter-function dependencies.
• Resolve multi-team bugs by root-cause analysis in areas like HBM, power/thermal, high-speed I/O, packaging.
• Steward the qualification playbook and capture reusable methodologies.
• Shape technical narrative for executive leadership with risks and mitigations.
• Mentor other Chip Leads and contribute to SCG-wide methodology.
• Lead Critical Debug and SCG Technical Execution forums; represent the chip externally.

Skills

SoC/ASIC architecture

HBM

SerDes

Power & Thermal

Packaging

Leadership without direct authority

Education

BS or MS in Electrical or Computer Engineering

Job description

NVIDIA Corporation in Santa Clara, CA is hiring a Chip Lead to serve as the technical lead for a major silicon program. You will be the primary technical partner across design, validation, software, and manufacturing, accountable for the chip's end-to-end technical integrity and for guiding multi-functional decisions.

The role demands >15 years in post-silicon bring-up, validation, or system integration within a major semiconductor company, with deep expertise in SoC/ASIC architecture and