Principal Chip Lead, Silicon Co-Design Group

NVIDIA Corporation

Santa Clara (CA)

Vor Ort

USD 232.000 - 368.000

Vollzeit

14 Tage+

Eine vollständige Bewerbung in einer Minute

Maßgeschneiderter Lebenslauf und Anschreiben – versandbereit.

Schaffe es an den ATS-Filtern vorbei

Benefits dieser Stelle

Equity
Benefits

Zusammenfassung

NVIDIA Corporation in Santa Clara, CA is hiring a Chip Lead to serve as the technical lead for a major silicon program. You will be the primary technical partner across design, validation, software, and manufacturing, accountable for the chip's end-to-end technical integrity and for guiding multi-functional decisions.

The role demands >15 years in post-silicon bring-up, validation, or system integration within a major semiconductor company, with deep expertise in SoC/ASIC architecture and

Qualifikationen

  • BS or MS in Electrical or Computer Engineering (or equivalent).
  • 15+ years of post-silicon bring-up, validation, or system integration leadership.
  • End-to-end understanding of SoC/ASIC architecture with cross-functional impact.
  • Proven ability to guide technical decisions across teams without direct reports.

Aufgaben

  • Serve as single technical point of contact for multi-functional decisions and trade-offs.
  • Co-lead feature integration from chip to system and surface inter-function dependencies.
  • Resolve multi-team bugs by root-cause analysis in areas like HBM, power/thermal, high-speed I/O, packaging.
  • Steward the qualification playbook and capture reusable methodologies.
  • Shape technical narrative for executive leadership with risks and mitigations.
  • Mentor other Chip Leads and contribute to SCG-wide methodology.
  • Lead Critical Debug and SCG Technical Execution forums; represent the chip externally.

Kenntnisse

SoC/ASIC architecture
HBM
SerDes
Power & Thermal
Packaging
Leadership without direct authority

Ausbildung

BS or MS in Electrical or Computer Engineering

Jobbeschreibung

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it.

What you’ll be doing:

You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track.

Day to day, you will:

  • Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.
  • Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.
  • Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging.
  • Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs.
  • Shape the program’s technical narrative by surfacing key risks, trade-offs, and mitigations as decision-ready options for executive leadership.
  • Mentor Chip Leads on adjacent silicon programs and contribute to SCG-wide methodology through post-mortems and write-ups.
  • Lead the program’s Critical Debug and SCG Technical Execution forums, and represent the chip externally with early insight into technical risks.
What we need to see:

BS or MS (or equivalent experience) in Electrical or Computer Engineering, plus over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company, including work on multiple shipped silicon products. 15+ years of experience. Strong end-to-end understanding of SoC and ASIC architecture, with recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging. Specific examples of silicon-level impact, such as faster bring-up, fewer escapes, yield recovery, or methodology contributions — especially turning ambiguous, multi‑team failure modes into root‑cause closure with reusable workarounds and write‑ups. A track record of guiding technical decisions across functional boundaries without direct reporting authority, and translating sophisticated silicon issues into clear options for executive audiences.

Ways to stand out from the crowd:
  • Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC.
  • Patents, conference papers, invited talks, or recognized contributions to silicon validation, post‑silicon debug, or co‑design integration are a plus.
  • A history of building and sharing technical methodology beyond a single program — reusable playbooks, debug frameworks, or standards adopted by other teams.
  • Hands‑on debug experience with HBM, high-speed I/O, power and thermal, or packaging is welcome.
  • Comfort working through ambiguity with globally distributed teams, and a habit of surfacing the right risks and recommendations to leadership without being asked.
  • Bonus points for using AI tools to lift team velocity, not just personal productivity.

If you build things others depend on and leave systems better than you found them, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 232,000 USD - 368,000 USD. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until September 27, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.

Hol dir deinen kostenlosen, vertraulichen Lebenslauf-Check.

oder ziehe deine Datei hierhin.

Similar jobs

Ähnliche Jobs, die dir auch gefallen könnten

Chip Lead, Silicon Co-Design Group
Chip Lead, Silicon Co-Design Group

NVIDIA • Santa Clara (CA)

Vor Ort
USD 196.000 - 368.000
Senior Manager, ASIC Chip Engineering
Senior Manager, ASIC Chip Engineering

NVIDIA • Santa Clara (CA)

Vor Ort
USD 232.000 - 368.000
Equity
Benefits
Post-Silicon Validation and Methodology Engineer
Post-Silicon Validation and Methodology Engineer

NVIDIA Corporation • Santa Clara (CA)

Vor Ort
USD 136.000 - 219.000
Equity
Benefits package
Chip Engineering Operations Program Manager
Chip Engineering Operations Program Manager

NVIDIA • Santa Clara (CA)

Vor Ort
USD 136.000 - 259.000
Senior Manager, System Co-Design Manager - SCG Team
Senior Manager, System Co-Design Manager - SCG Team

NVIDIA Corporation • Santa Clara (CA)

Vor Ort
USD 232.000 - 368.000
Senior System Integration and Validation Engineer
Senior System Integration and Validation Engineer

NVIDIA Corporation • Santa Clara (CA)

Vor Ort
USD 196.000 - 311.000
Equity
Flexible time off
Continuous learning
Senior Manager, System Co-Design Manager - SCG Team
Senior Manager, System Co-Design Manager - SCG Team

NVIDIA Gruppe • Santa Clara (CA)

Vor Ort
USD 232.000 - 368.000
Equity options
Generous benefits package
Senior System Integration and Validation Engineer
Senior System Integration and Validation Engineer

NVIDIA Gruppe • Santa Clara (CA)

Vor Ort
USD 168.000 - 311.000
Equity
Benefits
Manager, Chip Software
Manager, Chip Software

NVIDIA • Santa Clara (CA)

Vor Ort
USD 184.000 - 357.000
Equity
Senior Silicon Product Definition Engineer
Senior Silicon Product Definition Engineer

NVIDIA Corporation • Santa Clara (CA)

Vor Ort
USD 168.000 - 311.000
Equity