Career opportunity..!! Hardware Design and Failure Analysis Engineer Onsite San Jose CA Contract

Saransh Inc; San Jose (CA); Sur place; USD 140 000 - 190 000; Plein temps

Résumé du poste

Saransh Inc. in San Jose, CA is seeking a Hardware Design and Failure Analysis Engineer for onsite, 12+ month contract. You will lead high-speed hardware design with PCIe Gen4/5/6 and DDR4/5, ensuring robust power and signal integrity across complex boards.

You will direct external silicon suppliers and analytical labs for component-level FA, and translate technical results to executives and customers. A strong background in networking hardware is preferred, with hands-on experience rather than

Qualifications

• High-Speed hardware design experience with PCIe Gen4/5/6 and DDR4/5.
• Power and signal integrity analysis for complex power distribution networks.
• Experience directing external silicon suppliers and analytical labs for component-level FA.
• Strong communication skills for presenting technical findings to cross-functional leadership.

Responsabilités

• Lead high-speed hardware design with PCIe Gen4/5/6 and DDR4/5.
• Debug power integrity and signal integrity issues in complex boards.
• Direct external silicon suppliers and labs for component-level FA.
• Clearly communicate technical findings to executives and customers.
• Prefer candidates with networking hardware experience (routers/switches).
• Contribute hands-on design work rather than only troubleshooting failures.

Connaissances

PCIe Gen4/Gen5/Gen6

DDR4/DDR5

HBM

SerDes

Power integrity

Signal integrity

VRM transient analysis

Supplier engagement

Networking knowledge

Communication

Python automation

C automation

Outils

Python

C

Description du poste

Job Title: Role: : Hardware Design and Failure Analysis Engineer
Location: Onsite San Jose CA
Contract : 12+ Months

Job Description

• High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
• Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies.
• Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
• Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers
• Strong background in Networking, Routers, and Switches is highly preferred.
• Hands-on design experience with PCIe Gen4/Gen5/Gen6 and DDR4/DDR5 is essential.
• Candidates should have experience designing complex hardware platforms rather than only troubleshooting failures.

Preferred Qualifications

• Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.
• Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).
• Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.