ATE Test Engineer, Google Cloud

Socket.dev; Sunnyvale (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google in Sunnyvale, CA seeks an experienced silicon test engineer to help shape AI/ML hardware acceleration and verify complex digital designs focused on TPU architecture integration.

You will work with design and manufacturing teams to implement silicon test requirements, drive post-silicon verification best practices, and ensure high product integrity across mass fabrication.

Qualifications

• Bachelor's degree or equivalent in EE/CE/CS.
• 4 years of experience in test engineering or product engineering.
• Experience in ASIC or SoC test development, bring-up, or debug.
• Master's or PhD in EE/CE/CS with emphasis on computer architecture is preferred.
• Experience with test engineering, silicon quality/reliability is preferred.
• Experience with scan/ATPG test development or memory BIST test development and repair is preferred.
• Experience testing IPs such as PLLs, PMRO, temperature sensors, and eFuse is preferred.
• Familiarity with ATE from Advantest and Teradyne (EXA scale, UltraFlex+) is preferred.

Responsibilities

• Develop and drive implementation of silicon test requirements with internal design teams and external vendors.
• Develop and execute strategies for SoC product NPI, bring-up, verification, characterization, and qualification support, including bench test and troubleshooting.
• Leverage ATE test experience to drive quality improvements.
• Collaborate with design, DFT, and quality teams to drive best practices for post-silicon testing.
• Provide back-stop support for chip production, including test program upgrade and release procedures, data analytics, test time reduction, yield improvement, and RMA analysis.

Skills

ASIC/SoC test development

ATPG testing

IP testing (PLLs, PMRO, temp sensors)

ATE familiarity (Advantest/Teradyne)

Test engineering / product engineering

Education

Bachelor's degree or equivalent in EE/CE/CS

Master's or PhD in EE/CE/CS (computer architecture)

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience in test engineering or product engineering.
• Experience in ASIC or SoC test development, bring-up, or debug.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in test engineering, product engineering, or silicon quality/reliability.
• Experience with scan/ATPG test development or memory BIST test development and repair implementation.
• Experience testing IPs such as Phase-Locked Loops (PLLs), PVT sensors, temperature sensors, Process Monitor Ring Oscillator (PMRO), and eFuse.
• Familiarity with Automatic Test Equipment (ATE) from Advantest and Teradyne (e.g., EXA scale, UltraFlex+).

About the job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Google’s computing facilities are among the most advanced worldwide. In this role, you will help fabricate the custom processors that energize these hubs by steering the rollout of comprehensive automated evaluation solutions for high-volume manufacturing. You'll craft novel hardware and monitor it post-deployment to close the feedback loop back into architectural planning for upcoming hardware generations. You will integrate these components into machinery and guide industrial assessment to validate benchmark metrics while filtering out defective units. Finally, you will partner across internal groups to secure optimal verification depth throughout mass fabrication, guaranteeing product integrity.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Develop and drive implementation of silicon test requirements with internal design teams and external vendors.
• Participate in developing and executing strategies for SoC product NPI, bring‑up, verification, characterization, and qualification support, including bench test, troubleshooting, test coverage optimization, new product defective parts per million correlation, and product correlation between system and ATE.
  
• Leverage ATE test experience and expertise to drive quality improvements.
• Collaborate with design, DFT, and quality teams to drive best practices for post‑silicon testing.
• Provide back‑stop support for chip production, including test program upgrade and release procedures, volume data analytics, test time reduction, yield improvement, and Return Merchandise Authorization (RMA) analysis.