ASIC Technical Lead

Mosaic People Solutions; San Diego (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Mosaic People Solutions partners with a cutting-edge medical technology company in San Diego to recruit an experienced ASIC Technical Lead to own a high-channel-count neural recording mixed-signal ASIC program.

You will serve as the internal technical authority, drive pre-tapeout readiness, review SPICE/Cadence simulations, and lead architecture and design reviews with an external IC design partner.

Qualifications

• 5+ years of ASIC/SoC design or development experience.
• At least one full ASIC development cycle from concept to silicon/tapeout.
• Strong analog or mixed-signal IC design/verification background.
• Comfortable reviewing schematics and simulation results.
• Experience with an external design house, foundry or fab.
• Medical device or implantable electronics experience is a plus.

Responsibilities

• Own ASIC requirements and technical specifications.
• Lead design and architecture reviews.
• Review SPICE/Cadence simulations, DRC/LVS and DFT plans.
• Drive pre-tapeout technical readiness and sign-off.
• Support first-silicon bring-up and root-cause investigations.
• Manage technical risk across noise, power, matching and process corners.
• Lead technical review of any required respins.

Skills

ASIC/SoC design

Analog/mixed-signal design

Reviewing schematics & simulations

Collaboration with external design

Tools

Cadence

SPICE

DFT tooling

Job description

We're partnering with a cutting-edge medical technology company in San Diego that is looking for an experienced ASIC Technical Lead to take technical ownership of a highly sophisticated mixed-signal ASIC program.

This is a unique opportunity to serve as the internal technical authority for a high-channel-count neural recording chip being developed with an external IC design partner.

The role will be responsible for:

• Owning ASIC requirements and technical specifications
• Leading design and architecture reviews
• Reviewing SPICE/Cadence simulations, DRC/LVS and DFT plans
• Driving pre-tapeout technical readiness and sign-off
• Supporting first-silicon bring-up and root-cause investigations
• Managing technical risk across noise, power, matching and process corners
• Leading technical review of any required respins

Ideal background:

• 5+ years of ASIC/SoC design or development experience
• At least one full ASIC development cycle from concept through silicon/tapeoutli>
• Strong analog or mixed-signal IC design/verification background
• Comfortable reviewing and challenging schematics and simulation results
• Experience working with an external design house, foundry or fab
• Medical device or implantable electronics experience is a plus, but not required

This is not a role where you’re simply managing a vendor, they need someone technically deep enough to independently assess the design, identify issues, and ensure the silicon ultimately meets specification.