ASIC/RTL Design engineer - Sr Lead/Staff

Qualcomm; San Diego (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Qualcomm is seeking a Camera Design Lead/Staff in San Diego, responsible for designing and developing state-of-the-art SoCs for mobile camera applications. The ideal candidate will have a strong background in VLSI development and robust expertise in digital design using Verilog/SV. A collaborative team environment and good communication skills are essential for mentoring and ensuring effective project execution.

Qualifications

• 5-10 years experience in Hardware Engineering required.
• Experienced in ASIC design and development cycles.
• Good communication skills for effective team interaction.

Responsibilities

• Design and develop next generation SoCs for mobile phone cameras.
• Engage in all aspects of VLSI development cycle.
• Create unit level test plans and document designs.

Skills

Digital front end design

RTL microarchitecture

Verilog/SV coding

Bus protocols (AHB, AXI, NOC)

Low power design methodology

Formal verification

Good documentation

Education

Bachelor's degree in Computer Science

Master's degree in Electrical/Electronics Engineering

PhD in related field

Tools

Spyglass

Cadence LEC

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Function : Camera Design Lead/Staff

Candidate will be responsible for design/developing next generation SoCs sub systems for mobile phone camera . Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, Synthesis/PD interaction and design convergence.

Skills/Experience

5-10 years with Masters (6 to 10 years with Bachelors)

Solid experience in digital front end design for ASICs
Solid Expertise in RTL microarchitecture and design coding in Verilog/SV for complex designs with multiple clock and power domains
Expertise with various bus protocols like AHB, AXI and NOC designs

Experience in low power design methodology and clock domain crossing designs
Understanding of full RTL to GDS flow to interact with DFT and PD teams

Experience in Tools like Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC

Experience in mobile Multimedia/Camera design is a plus

DSP /ISP knowledge is a plus.

Working knowledge of timing closure is a plus
Expertise in Perl, TCL language is a plus
Expertise in post-Si debug is a plus

Good documentation skills
Ability to create unit level test plan

General

Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members.

Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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