ASIC Implementation Engineer STA

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grant

401(k) matching

Medical/dental/vision

Job summary

Broadcom is seeking an experienced Full-Chip STA Engineer to own timing closure for ASICs across PVT corners, ensuring performance targets are met.

You will develop and validate SDCs, work with RTL, PD and DFT teams, and apply advanced timing concepts like AOCV/POCV and crosstalk. This role offers a competitive salary, annual bonus, equity options and comprehensive benefits.

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer engineering.
• A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools.
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints.
• Well versed with scripting languages like TCL and Python, PERL, or Shell.
• Strong problem solving skills with attention to every technical aspect.
• Be a strong team player with clear and precise communication skills.
• EDA Tool Expertise: Expert proficiency in industry-standard sign-off tool.

Responsibilities

• Own the final timing closure for ASIC across PVT corners.
• Develop, validate, and maintain SDC files for multiple modes.
• Incorporate sign-off corners, margins, and derates into timing flows.
• Apply advanced timing concepts: AOCV/POCV, crosstalk, IR-drop aware STA.
• Perform MMMC analysis across hundreds of timing scenarios.
• Automate ECOs to fix setup, hold, and transition violations.
• Script in Tcl, Python, and Perl to automate analysis.
• Collaborate with RTL, Physical Design, and DFT teams.

Education

Bachelor’s degree in Electrical Engineering or Computer engineering

Job description

USA-CA San Jose Innovation Drive

Full time

R026202

Job Description:

The Full Chip Static Timing Analysis (STA) Engineer is responsible for ensuring that ASIC meets its performance targets and timing requirements across all operating conditions.

Key Responsibilities:

• Full-Chip Timing Sign-off: Own the final timing closure for ASIC, performing quality checks across all process, voltage, and temperature (PVT) corners
• Constraint Development: Author, validate, and maintain SDC for various modes, including functional and test modes (Scan, MBIST,ATPG)
• Analyze foundry guidelines and work with the team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies
• Advanced Timing Concepts: Deep knowledge of On-Chip Variation (AOCV/POCV), Signal Integrity (crosstalk), and IR-drop aware STA
• Multi-Mode Multi-Corner (MMMC) Analysis: Manage and analyze hundreds of timing scenarios to ensure reliability across diverse operating environments
• Timing ECOs: Automate, generate and implement ECOs to fix setup, hold, and transition violations in the design cycle
• Scripting: High proficiency in Tcl (primary for EDA tools), Python, and Perl for automating analysis flows and data mining.
• Cross-Functional Collaboration: Partner with RTL, Physical Design, and DFT teams to resolve complex timing issues and define guard-banding requirements
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
• Document best practices and lessons learned to drive continuous improvements in future projects

Qualifications:

• Bachelor’s degree in Electrical Engineering or Computer engineering
• A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills
• EDA Tool Expertise: Expert proficiency in industry-standard sign-off tool

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom!

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

For more information please visit our video library (http://www.broadcom.com/videos) and check out our Connected by Broadcom (https://www.broadcom.com/support/resources/video-webinar-library?channel=5c9658f7c1d34eca91c6cc16178e5b1b&video=7d72b04ea50046a394e682fab640ce20) series.

Follow us on Linked In Broadcom Inc (https://www.linkedin.com/company/broadcom) .