ASIC & FPGA Design Engineer Sr - E3

Lockheed Martin Corporation; Grand Prairie (TX); On-site; USD 98,000 - 182,000; Full time

Benefits offered by this job

Medical benefits

Flexible work arrangements (e.g., 4x10

401(k) match

Paid time off

Job summary

Lockheed Martin Corporation in Dallas, TX seeks a Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team. You will define architecture, write RTL (VHDL/Verilog/SystemVerilog), and drive timing closure on target devices.

You will create verification environments, perform timing/power analyses, and lead hardware-in-the-loop testing. Collaboration across multiple engineering disciplines is essential, with mentoring for junior engineers.

Qualifications

• Bachelor of Science in Electrical Engineering or closely related STEM field; Master’s preferred
• 3+ years FPGA design and verification experience
• HDL programming with VHDL/Verilog/SystemVerilog
• Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design
• Experience with FPGA simulation tools (Synopsys VCS)
• Knowledge of timing analysis, clock domain crossing and signal integrity
• Experience with high-speed interfaces (AXI, PCIe, Ethernet)
• US citizenship and ability to obtain DoD clearance

Responsibilities

• Define architecture and RTL for ASIC/FPGA components
• Develop synthesis, place and route, timing closure strategies
• Create test plans and verification environments (UVM, SystemC)
• Lead hardware-in-the-loop testing and board-level debugging
• Collaborate with systems, software, hardware, and QA teams
• Mentor junior engineers and promote best practices in FPGA development

Skills

HDL programming

FPGA design

Timing analysis

High-speed interfaces

Mentoring

Education

B.Sc Electrical Engineering

M.S. preferred

Tools

Vivado

Vitis

Vitis HLS

Synopsys VCS

Synplify

Job description

Standard Job Description

You will be the Senior ASIC &FPGA Design Engineer for the Programmable Logic Design team within Lockheed Martin Missiles and Fire Control (MFC). Our team creates, prototypes, and fields precision engagement aerospace and defense systems for the U.S. and allied militaries, delivering cutting edge digital solutions that protect the warfighter.

What You Will Be Doing

• Define architecture and design specifications for ASIC/FPGA components; write clean, maintainable RTL (VHDL, Verilog, SystemVerilog) that meets performance, power and reliability goals.
• Develop synthesis, place and route and timing closure strategies to guarantee deterministic operation on target devices.
• Create comprehensive test plans, simulation models and verification environments (UVM, SystemC, Python based testbenches) to validate functional correctness and timing margins.
• Lead hardware in the loop (HIL) testing, board level debugging and integration with subsystem hardware.
• Conduct timing analysis, power budgeting and resource utilization studies to optimize device selection and FPGA utilization.
• Manage configuration control using GitLab (or equivalent), maintain version controlled repositories and ensure full traceability of all artifacts.
• Produce complete design documentation—specifications, test plans, verification reports and release packages that complies with aerospace standards.
• Collaborate with systems, software, hardware, mechanical, test, manufacturing and quality teams to guarantee seamless integration and milestone compliance.
• Mentor junior engineers, championing best practices in FPGA development, verification and configuration management.

Why Join Us

Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you.

We offer flexible work schedules to comprehensive benefits investing in your future and security, Learn more about Lockheed Martin’s comprehensive benefits package here.

Further Information About This Opportunity

This position is in Dallas. Discover more about our Dallas, Texas location.

MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance.

Basic Qualifications

• Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree preferred
• Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline
• Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog
• Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology
• Experience with FPGA simulation tools such as Synopsys VCS
• Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity
• Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols
• Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators
• Familiarity with Synopsys EDA tools
• Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance

Desired Skills

• LM/MFC design experience and missile program experience
• Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets
• Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP
• Experience implementing NSA algorithms (e.g., AES, counter mode)
• Experience managing configuration control (GitLab preferred)
• Experience with Vivado and Vitis FPGA toolsets
• Experience with UVM and Simulink/HDL Coder integration
• Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment
• Experience with troubleshooting and debugging at board level, including FPGA validation
• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
• Strong communication, collaboration, and presentation abilities
• Controls and digital loop-closure application knowledge
• Networking proficiency with Ethernet switches, routers, firewalls, and debugging tools (tcpdump, Wireshark)
• Active DoD Secret or Top Secret clearance

Pay Information

Full-Time Salary Range: $98100.00 - $182100.00

At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally.

The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only.Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.

Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.

• Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.
• For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.